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* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-106-7/+7
| | | | llvm-svn: 163547
* Disable stack coloring because it makes dragonegg fail bootstrapping.Nadav Rotem2012-09-101-1/+1
| | | | llvm-svn: 163545
* [ms-inline asm] Pass the correct AsmVariant to the PrintAsmOperand() functionChad Rosier2012-09-103-7/+10
| | | | | | and update the printOperand() function accordingly. llvm-svn: 163544
* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-1/+4
| | | | llvm-svn: 163542
* Enable stack coloring.Nadav Rotem2012-09-101-1/+1
| | | | llvm-svn: 163539
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
| | | | | | | | | | | | The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
* [Object] Extract Elf_Ehdr. Patch by Hemant Kulkarni!Michael J. Spencer2012-09-101-2/+1
| | | | llvm-svn: 163532
* Stack Coloring: Handle the case where END markers come before BEGIN markers ↵Nadav Rotem2012-09-101-0/+12
| | | | | | properly. llvm-svn: 163530
* Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao2012-09-103-7/+15
| | | | | | - Fix an remaining issue of PR11674 as well llvm-svn: 163528
* Add "blocked" heuristic to the Hexagon MI scheduler.Sergei Larin2012-09-102-177/+269
| | | | | | Improve AQ instruction selection in the Hexagon MI scheduler. llvm-svn: 163523
* Fold multiply by 0 or 1 when in UnsafeFPMath mode in SelectionDAG::getNode().Michael Ilseman2012-09-101-0/+18
| | | | | | This folding happens as early as possible for performance reasons, and to make sure it isn't foiled by other transforms (e.g. forming FMAs). llvm-svn: 163519
* whitespaceMichael Ilseman2012-09-101-10/+10
| | | | llvm-svn: 163518
* Add boolean simplification support from CMOVMichael Liao2012-09-101-12/+42
| | | | | | | | - If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. llvm-svn: 163516
* Fix an assertion failure when optimising a shufflevector incorrectly into ↵James Molloy2012-09-102-10/+12
| | | | | | concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types. llvm-svn: 163511
* Minor cleanup. No functional change.Nadav Rotem2012-09-101-3/+3
| | | | llvm-svn: 163510
* Stack Coloring: Debug prints to print the slot number and not the array index.Nadav Rotem2012-09-101-1/+2
| | | | llvm-svn: 163509
* Stack Coloring: When searching for disjoint regions, do not compare ↵Nadav Rotem2012-09-101-1/+1
| | | | | | intervals twice or to theirself. llvm-svn: 163508
* Stack Coloring: Add support for multiple regions of the same slot, within a ↵Nadav Rotem2012-09-101-23/+33
| | | | | | single basic block. llvm-svn: 163507
* The VPSHUFB 256-bit instruction may be generated when one of input vector is ↵Elena Demikhovsky2012-09-101-4/+15
| | | | | | | | undefined or zeroinitializer. I've added the "zeroinitializer" case in this patch. llvm-svn: 163506
* Make helper function static.Benjamin Kramer2012-09-101-2/+1
| | | | llvm-svn: 163504
* Move bypassSlowDivision into the llvm namespace.Benjamin Kramer2012-09-101-4/+6
| | | | llvm-svn: 163503
* c bindings: revert LLVMConstInlineAsm to always use the default asm dialect.Benjamin Kramer2012-09-101-4/+2
| | | | | | | | - The C API should be stable - InlineAsm::AsmDialect is not exposed to C - The function didn't match the prototype so this was unreachable code llvm-svn: 163502
* Fix a typo in the comment.Nadav Rotem2012-09-101-2/+2
| | | | llvm-svn: 163496
* Add an assertion that the frame index is indeed inside the declared lifetime ↵Nadav Rotem2012-09-101-0/+16
| | | | | | region. llvm-svn: 163495
* Teach the DAGBuilder about lifetime markers which are generated from PHINodes.Nadav Rotem2012-09-101-18/+22
| | | | llvm-svn: 163494
* Fix style issues from r163302 pointed out by Evan.Hans Wennborg2012-09-101-18/+15
| | | | llvm-svn: 163491
* Move spaces to the right places. No functionality change.Nick Lewycky2012-09-091-4/+4
| | | | llvm-svn: 163485
* Add missing space before {. No functionality change.Nick Lewycky2012-09-091-1/+1
| | | | llvm-svn: 163484
* Teach DAG combiner to constant fold fneg of a BUILD_VECTOR of constants.Craig Topper2012-09-091-1/+25
| | | | llvm-svn: 163483
* DSE: Poking holes into a SetVector is expensive, avoid it if possible.Benjamin Kramer2012-09-091-5/+5
| | | | llvm-svn: 163480
* LiveVariables: Compute a set of defs and kills to speed up updating LV ↵Benjamin Kramer2012-09-091-4/+30
| | | | | | | | | | | | | | | during critical edge splitting. Previously we checked if the register is def'd in a block via the def/use list a nd walked the list of kills to check if the register is killed in a block. Both of these checks can be made much cheaper by walking the block first and recording all defs and kills. This reduces the compile time of the test case from PR13651 from 40s to 15s at -O2. The compile time is still dominated by LV updating but now the main culprit is SparseBitVector's slowness. llvm-svn: 163478
* Add instruction selection for ffloor of vectors when SSE4.1 or AVX is enabled.Craig Topper2012-09-082-20/+41
| | | | llvm-svn: 163473
* Use 256-bit alignment for constant pool value for 256-bit vector FNEG lowering.Craig Topper2012-09-081-2/+3
| | | | llvm-svn: 163463
* Add support for lowering FABS of vector types.Craig Topper2012-09-081-12/+25
| | | | llvm-svn: 163461
* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-082-0/+2
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* Add operator< for FoldingSetNodeID.Ted Kremenek2012-09-081-0/+18
| | | | llvm-svn: 163454
* Remove an incorrect assert during branch weight propagation.Andrew Trick2012-09-081-1/+0
| | | | | | Patch and test case by Alastair Murray! llvm-svn: 163437
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-077-12/+20
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. llvm-svn: 163420
* Fix indent.Chad Rosier2012-09-071-2/+2
| | | | llvm-svn: 163416
* Contrary to what the documentation says, .lcomm alignment on COFF is in ↵Benjamin Kramer2012-09-071-1/+1
| | | | | | bytes, not power of 2. llvm-svn: 163405
* Update function names to conform to guidelines. No functional change intended.Chad Rosier2012-09-072-49/+48
| | | | llvm-svn: 163401
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-0710-21/+28
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-071-5/+6
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. llvm-svn: 163390
* MipsAsmParser: Fix a couple of string use-after-frees and misuses of classof.Benjamin Kramer2012-09-071-8/+8
| | | | llvm-svn: 163383
* SimplifyCFG: ValidLookupTableConstant should be staticHans Wennborg2012-09-071-1/+1
| | | | llvm-svn: 163378
* Stop emitting lifetime region info when stack coloring is not enabled in O0Michael Liao2012-09-071-0/+6
| | | | | | - this should fix PR13780 llvm-svn: 163370
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-071-0/+20
| | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
* The Mips standalone assembler intial directive support.Jack Carter2012-09-071-0/+43
| | | | | | | | | | Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic llvm-svn: 163364
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-072-7/+220
| | | | | | | Test cases included Contributer: Vladimir Medic llvm-svn: 163363
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