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* RAGreedy: Keep track of allocated PhysRegs internallyMatthias Braun2015-07-142-18/+32
| | | | | | | | | | | Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed() anymore. This bitset changes function-global state and is set by the VirtRegRewriter anyway. Simply use a bitvector private to RAGreedy. Differential Revision: http://reviews.llvm.org/D10910 llvm-svn: 242169
* Add missing builtins to the PPC back end for ABI compliance (vol. 4)Nemanja Ivanovic2015-07-141-0/+6
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D11183 Back end portion of the fourth round of additions to altivec.h. llvm-svn: 242167
* PrologEpilogInserter: Rewrite API to determine callee save regsiters.Matthias Braun2015-07-1426-134/+223
| | | | | | | | | | | | | | | | This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan(): - Rename the function to determineCalleeSaves() - Pass a bitset of callee saved registers by reference, thus avoiding the function-global PhysRegUsed bitset in MachineRegisterInfo. - Without PhysRegUsed the implementation is fine tuned to not save physcial registers which are only read but never modified. Related to rdar://21539507 Differential Revision: http://reviews.llvm.org/D10909 llvm-svn: 242165
* AArch64: add rev64 alias for 64-bit rev instruction.Tim Northover2015-07-141-0/+2
| | | | | | | It could be useful to assembly programmers and makes the permitted variants a little more uniform. llvm-svn: 242164
* [Hexagon] Generate "extract" instructions more aggressivelyKrzysztof Parzyszek2015-07-143-13/+278
| | | | | | | Generate extract instructions (via intrinsics) before the DAG combiner folds shifts into unrecognizable forms. llvm-svn: 242163
* ARMAsmParser: Take MCInst param by const-refHans Wennborg2015-07-141-8/+9
| | | | | | (Broken out from http://reviews.llvm.org/D11167) llvm-svn: 242160
* Caused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9Alexandros Lamprineas2015-07-141-96/+83
| | | | | | | | Revert "-Added API for retrieving the default FPU of a CPU from TargetParser." This reverts commit 01199ab0c6ff2d5c4f6b2c05a95ec011e41c4669. llvm-svn: 242147
* AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructionsTom Stellard2015-07-141-6/+27
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11061 llvm-svn: 242146
* Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to ↵Aaron Ballman2015-07-141-1/+1
| | | | | | 'int16_t' and truncation of constant value. NFC intended. llvm-svn: 242145
* -Added API for retrieving the default FPU of a CPU from TargetParser.Alexandros Lamprineas2015-07-141-83/+96
| | | | | | | | -Implemented as a table lookup. Change-Id: Ibf7217f6bd2769e9c06835a5aede3d072dee6757 Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242141
* [mips] Fix li/la differences between IAS and GAS.Daniel Sanders2015-07-141-82/+83
| | | | | | | | | | | | | | | | | | | Summary: - Signed 16-bit should have priority over unsigned. - For la, unsigned 16-bit must use ori+addu rather than directly use ori. - Correct tests on 32-bit immediates with 64-bit predicates by sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000) should be true and use addiu. Also split li/la testing into separate files due to their size. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10967 llvm-svn: 242139
* [PM/AA] Reformat GlobalsModRef so that subsequent patches I make hereChandler Carruth2015-07-141-155/+160
| | | | | | don't continually introduce formatting deltas. NFC llvm-svn: 242129
* [SROA] Don't de-atomic volatile loads and storesDavid Majnemer2015-07-141-6/+15
| | | | | | | | | | | Volatile loads and stores are made visible in global state regardless of what memory is involved. It is not correct to disregard the ordering and synchronization scope because it is possible to synchronize with memory operations performed by hardware. This partially addresses PR23737. llvm-svn: 242126
* Generate correct asm info for mingw and cygwin ARM targets.Yaron Keren2015-07-141-2/+2
| | | | | | | | | http://reviews.llvm.org/D11075 Patch by Martell Malone Reviewed by Reid Kleckner llvm-svn: 242123
* Prune trailing whitespaces and CRs.NAKAMURA Takumi2015-07-141-23/+23
| | | | llvm-svn: 242117
* Revert "LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization"Matthias Braun2015-07-141-150/+74
| | | | | | | | Accidental commit, needs review first. This reverts commit r242107. llvm-svn: 242108
* LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalizationMatthias Braun2015-07-141-74/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Factor out code to query and modify the sign bit of a floatingpoint value as an integer. This also works if none of the targets integer types is big enough to hold all bits of the floatingpoint value. - Legalize FABS(x) as FCOPYSIGN(x, 0.0) if FCOPYSIGN is available, otherwise perform bit manipulation on the sign bit. The previous code used "x >u 0 ? x : -x" which is incorrect for x being -0.0! It also takes 34 instructions on ARM Cortex-M4. With this patch we only require 5: vldr d0, LCPI0_0 vmov r2, r3, d0 lsrs r2, r3, #31 bfi r1, r2, #31, #1 bx lr (This could be further improved if the compiler would recognize that r2, r3 is zero). - Only lower FCOPYSIGN(x, y) = sign(x) ? -FABS(x) : FABS(x) if FABS is available otherwise perform bit manipulation on the sign bit. - Perform the sign(x) test by masking out the sign bit and comparing with 0 rather than shifting the sign bit to the highest position and testing for "<s 0". For x86 copysignl (on 80bit values) this gets us: testl $32768, %eax rather than: shlq $48, %rax sets %al testb %al, %al llvm-svn: 242107
* Add capability to get and set the personalitty function from the C APIAndrew Wilkins2015-07-141-0/+8
| | | | | | | | | | | | | | | Summary: The capability was lost with D10429 where the personality function was set at function level rather than landing pad level. Now there is no way to get/set the personality function from the C API. That is a problem. Note that the whole thing could be avoided by improving the C API testing, as started by D10725 Reviewers: chandlerc, bogner, majnemer, andrew.w.kaylor, rafael, rnk, axw Subscribers: rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D10946 llvm-svn: 242104
* Add a herper function. NFC.Rafael Espindola2015-07-141-8/+7
| | | | llvm-svn: 242100
* MIR Serialization: Serialize the variable sized stack objects.Alex Lorenz2015-07-142-4/+11
| | | | llvm-svn: 242095
* Update enforceKnownAlignment after the isWeakForLinker semantic changeReid Kleckner2015-07-141-7/+4
| | | | | | | | | | | | | Previously we would refrain from attempting to increase the linkage of available_externally globals because they were considered weak for the linker. Now they are treated more like a declaration instead of a weak definition. This was causing SSE alignment faults in Chromuim, when some code assumed it could increase the alignment of a dllimported global that it didn't control. http://crbug.com/509256 llvm-svn: 242091
* MIR Serialization: Serialize the sub register indices.Alex Lorenz2015-07-134-3/+53
| | | | | | | | This commit serializes the sub register indices from the register machine operands. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242084
* Fix reading archive members with / in the name.Rafael Espindola2015-07-131-3/+3
| | | | | | This is important for thin archives. llvm-svn: 242082
* [PPC64LE] More improvements to VSX swap optimizationBill Schmidt2015-07-131-21/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows VSX swap optimization to succeed more frequently. Specifically, it is concerned with common code sequences that occur when copying a scalar floating-point value to a vector register. This patch currently handles cases where the floating-point value is already in a register, but does not yet handle loads (such as via an LXSDX scalar floating-point VSX load). That will be dealt with later. A typical case is when a scalar value comes in as a floating-point parameter. The value is copied into a virtual VSFRC register, and then a sequence of SUBREG_TO_REG and/or COPY operations will convert it to a full vector register of the class required by the context. If this vector register is then used as part of a lane-permuted computation, the original scalar value will be in the wrong lane. We can fix this by adding a swap operation following any widening SUBREG_TO_REG operation. Additional COPY operations may be needed around the swap operation in order to keep register assignment happy, but these are pro forma operations that will be removed by coalescing. If a scalar value is otherwise directly referenced in a computation (such as by one of the many XS* vector-scalar operations), we currently disable swap optimization. These operations are lane-sensitive by definition. A MentionsPartialVR flag is added for use in each swap table entry that mentions a scalar floating-point register without having special handling defined. A common idiom for PPC64LE is to convert a double-precision scalar to a vector by performing a splat operation. This ensures that the value can be referenced as V[0], as it would be for big endian, whereas just converting the scalar to a vector with a SUBREG_TO_REG operation leaves this value only in V[1]. A doubleword splat operation is one form of an XXPERMDI instruction, which takes one doubleword from a first operand and another doubleword from a second operand, with a two-bit selector operand indicating which doublewords are chosen. In the general case, an XXPERMDI can be permitted in a lane-swapped region provided that it is properly transformed to select the corresponding swapped values. This transformation is to reverse the order of the two input operands, and to reverse and complement the bits of the selector operand (derivation left as an exercise to the reader ;). A new test case that exercises the scalar-to-vector and generalized XXPERMDI transformations is added as CodeGen/PowerPC/swaps-le-5.ll. The patch also requires a change to CodeGen/PowerPC/swaps-le-3.ll to use CHECK-DAG instead of CHECK for two independent instructions that now appear in reverse order. There are two small unrelated changes that are added with this patch. First, the XXSLDWI instruction was incorrectly omitted from the list of lane-sensitive instructions; this is now fixed. Second, I observed that the same webs were being rejected over and over again for different reasons. Since it's sufficient to reject a web only once, I added a check for this to speed up the compilation time slightly. llvm-svn: 242081
* Loop idiom recognizer was replacing too many uses of popcount.Pete Cooper2015-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When spotting that a loop can use ctpop, we were incorrectly replacing all uses of a value with a value derived from ctpop. The bug here was exposed because we were replacing a use prior to the ctpop with the ctpop value and so we have a use before def, i.e., we changed %tobool.5 = icmp ne i32 %num, 0 store i1 %tobool.5, i1* %ptr br i1 %tobool.5, label %for.body.lr.ph, label %for.end to store i1 %1, i1* %ptr %0 = call i32 @llvm.ctpop.i32(i32 %num) %1 = icmp ne i32 %0, 0 br i1 %1, label %for.body.lr.ph, label %for.end Even if we inserted the ctpop so that it dominates the store here, that would still be incorrect. The store doesn’t want the result of ctpop. The fix is very simple, and involves replacing only the branch condition with the ctpop instead of all uses. Reviewed by Hal Finkel. llvm-svn: 242068
* [WinEH] Emit the LSDA even if no lpads remain but outlining occurredReid Kleckner2015-07-131-6/+14
| | | | | | | | | | | | | | | The outlined funclets call intrinsics which reference labels from the LSDA. This situation can easily arise in small functions with a single cleanup at -O0, where Clang marks a definition as nounwind, and then WinEHPrepare "discovers" that the landingpad is dead by accident and deletes it. We now need to ask the LLVM IR Function for it's personality directly, rather than going through MachineModuleInfo. Fixes PR23892. llvm-svn: 242063
* [Hexagon] Move BitTracker into the llvm namespace and remove redundant ↵Benjamin Kramer2015-07-134-64/+52
| | | | | | | | qualifications No functional change intended. llvm-svn: 242062
* Add support deterministic output in llvm-ar and make it the default.Rafael Espindola2015-07-132-18/+45
| | | | llvm-svn: 242061
* AMDGPU: Minor cleanups to always inline passMatt Arsenault2015-07-131-7/+4
| | | | llvm-svn: 242053
* [MC] Correctly escape .safeseh's symbolDavid Majnemer2015-07-131-1/+2
| | | | | | This fixes PR24107. llvm-svn: 242050
* Enable partial and runtime loop unrolling for NVPTX.Mark Heffernan2015-07-132-0/+14
| | | | | | | | | Enable partial and runtime loop unrolling for NVPTX backend via TTI::UnrollingPreferences with a small threshold. This partially unrolls small loops which are often unrolled by the PTX to SASS compiler and unrolling earlier can be beneficial. llvm-svn: 242049
* Enable runtime unrolling with unroll pragma metadataMark Heffernan2015-07-131-2/+4
| | | | | | | | | | Enable runtime unrolling for loops with unroll count metadata ("#pragma unroll N") and a runtime trip count. Also, do not unroll loops with unroll full metadata if the loop has a runtime loop count. Previously, such loops would be unrolled with a very large threshold (pragma-unroll-threshold) if runtime unrolled happened to be enabled resulting in a very large (and likely unwise) unroll factor. llvm-svn: 242047
* Service the doxygen comments in DwarfUnit and DwarfDebug.Adrian Prantl2015-07-132-148/+151
| | | | llvm-svn: 242046
* MIR Serialization: Serialize the fixed stack objects.Alex Lorenz2015-07-132-1/+36
| | | | | | | | | | | | | This commit serializes the fixed stack objects, including fixed spill slots. The fixed stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset, and alignment. The objects that aren't spill slots also serialize the isImmutable and isAliased flags. The fixed stack objects are a part of the machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242045
* [WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk nameReid Kleckner2015-07-131-3/+5
| | | | | | Add another C++ 32-bit EH table test. llvm-svn: 242044
* Remove macro guards for extern template instantiations.Benjamin Kramer2015-07-133-29/+25
| | | | | | | This is a C++11 feature that both GCC and MSVC have supported as ane extension long before C++11 was approved. llvm-svn: 242042
* Avoid using Loop::getSubLoopsVector.Benjamin Kramer2015-07-132-7/+7
| | | | | | | Passes should never modify it, just use the const version. While there reduce copying in LoopInterchange. No functional change intended. llvm-svn: 242041
* Fix handling of the 'n' asm constraint with invalid operands.James Y Knight2015-07-131-2/+2
| | | | | | | | | | It had accidently accepted a symbol+offset value (and emitted incorrect code for it, keeping only the offset part) instead of properly reporting the constraint as invalid. Differential Revision: http://reviews.llvm.org/D11039 llvm-svn: 242040
* AMDGPU/SI: Select mad patterns to v_mac_f32Tom Stellard2015-07-137-8/+141
| | | | | | | | | The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038
* ARM: Fix cttz expansion on vector types.Logan Chien2015-07-131-2/+98
| | | | | | | | | | | | The 64/128-bit vector types are legal if NEON instructions are available. However, there was no matching patterns for @llvm.cttz.*() intrinsics and result in fatal error. This commit fixes the problem by lowering cttz to: a. ctpop((x & -x) - 1) b. width - ctlz(x & -x) - 1 llvm-svn: 242037
* [ARM] Handle commutativity when converting to tADDhirr in Thumb2Scott Douglass2015-07-131-3/+11
| | | | | | | | Also, run thumb_rewrite.s tests in Thumb2 now that they pass. Differential Revision: http://reviews.llvm.org/D11132 llvm-svn: 242036
* [ARM] Add Thumb2 ADD with SP narrowing from 3 operand to 2Scott Douglass2015-07-131-5/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D11131 llvm-svn: 242035
* [ARM] Small refactor of tryConvertingToTwoOperandForm (nfc)Scott Douglass2015-07-131-7/+10
| | | | | | | | | Also, add more Thumb2 ADD tests requested during review of http://reviews.llvm.org/D11053. Differential Revision: http://reviews.llvm.org/D11130 llvm-svn: 242034
* Cleanup after r241809 - remove uncessary call to std::sortSilviu Baranga2015-07-131-10/+5
| | | | | | | | | | | | | | Summary: The iteration order within a member of DepCands is deterministic and therefore we don't have to sort the accesses within a member. We also don't have to copy the indices of the pointers into a vector, since we can iterate over the members of the class. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11145 llvm-svn: 242033
* Remove unused variable.Rafael Espindola2015-07-131-1/+0
| | | | | | Sorry I missed it in the previous commit. llvm-svn: 242032
* Aliases don't have available_externally linkage.Rafael Espindola2015-07-131-11/+0
| | | | | | | Allowing that is probably a good idea, but currently we don't, so this is dead code. llvm-svn: 242031
* Don't change the visibility when converting a definition to a declaration.Rafael Espindola2015-07-132-3/+1
| | | | llvm-svn: 242030
* Removing several -Wunused-but-set-variable warnings; NFC intended.Aaron Ballman2015-07-131-26/+0
| | | | llvm-svn: 242028
* Print the visibility of available_externally functions.Rafael Espindola2015-07-131-1/+1
| | | | | | We were already printing it for declarations, but not available_externally. llvm-svn: 242027
* Revert r241981 "Revert "Revert r236894 "[BasicAA] Fix zext & sext handling"""Manuel Klimek2015-07-131-199/+60
| | | | | | The repros from PR23626 still fail. llvm-svn: 242025
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