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* [X86][SSE] lowerVectorShuffleAsPermuteAndUnpack tidyup. NFCI.Simon Pilgrim2016-07-171-10/+7
| | | | | | | | Moved unpack type determination into TryUnpack lambda. Added missing comment describing lowerVectorShuffleAsPermuteAndUnpack call. llvm-svn: 275708
* [ThinLTO] Perform profile-guided indirect call promotionTeresa Johnson2016-07-173-13/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To enable profile-guided indirect call promotion in ThinLTO mode, we simply add call graph edges for each profitable target from the profile to the summaries, then the summary-guided importing will consider the callee for importing as usual. Also we need to enable the indirect call promotion pass creation in the PassManagerBuilder when PerformThinLTO=true (we are in the ThinLTO backend), so that the newly imported functions are considered for promotion in the backends. The IC promotion profiles refer to callees by GUID, which required adding GUIDs to the per-module VST in bitcode (and assigning them valueIds similar to how they are assigned valueIds in the combined index). Reviewers: mehdi_amini, xur Subscribers: mehdi_amini, davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21932 llvm-svn: 275707
* Address review comments.Teresa Johnson2016-07-171-0/+8
| | | | llvm-svn: 275706
* Refactor indirect call promotion profitability analysis (NFC)Teresa Johnson2016-07-171-8/+0
| | | | | | | | | | | | | | | Summary: Refactored the profitability analysis out of the IC promotion pass and into lib/Analysis so that it can be accessed by the summary index builder in a follow-on patch to enable IC promotion in ThinLTO (D21932). Reviewers: davidxl, xur Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22182 llvm-svn: 275705
* test commitGuy Blank2016-07-171-1/+1
| | | | llvm-svn: 275703
* [PM] Convert IVUsers analysis to new pass manager.Dehao Chen2016-07-166-43/+68
| | | | | | | | | | | | Summary: Convert IVUsers analysis to new pass manager. Reviewers: davidxl, silvas Subscribers: junbuml, sanjoy, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22434 llvm-svn: 275698
* [InstCombine] allow X + signbit --> X ^ signbit for vector splatsSanjay Patel2016-07-161-3/+10
| | | | llvm-svn: 275691
* IPRA: avoid double query to the map (NFC)Mehdi Amini2016-07-161-2/+3
| | | | llvm-svn: 275689
* [InstCombine] reassociate logic ops with constants separated by a zextSanjay Patel2016-07-161-0/+49
| | | | | | | | | | | | This is a partial implementation of a general fold for associative+commutative operators: (op (cast (op X, C2)), C1) --> (cast (op X, op (C1, C2))) (op (cast (op X, C2)), C1) --> (op (cast X), op (C1, C2)) There are 7 associative operators and 13 cast types, so this could potentially go a lot further. Differential Revision: https://reviews.llvm.org/D22421 llvm-svn: 275684
* Revert "Revert r275027 - Let FuncAttrs infer the 'returned' argument attribute"Hal Finkel2016-07-161-0/+50
| | | | | | | | | | | | | | | | This reverts commit r275042; the initial commit triggered self-hosting failures on ARM/AArch64. James Molloy identified the problematic backend code, which has been disabled in r275677. Trying again... Original commit message: Let FuncAttrs infer the 'returned' argument attribute A function can have one argument with the 'returned' attribute, indicating that the associated argument is always the return value of the function. Add FuncAttrs inference logic. llvm-svn: 275678
* Disable this-return argument forwarding on ARM/AArch64Hal Finkel2016-07-162-2/+16
| | | | | | | | | | | r275042 reverted function-attribute inference for the 'returned' attribute because the feature triggered self-hosting failures on ARM and AArch64. James Molloy determined that the this-return argument forwarding feature, which directly ties the returned input argument to the returned value, was the cause. It seems likely that this forwarding code contains, or triggers, a subtle bug. Disabling for now until we can track that down. llvm-svn: 275677
* Re-commit [AMDGPU] Add metadata for runtimeYaxun Liu2016-07-163-0/+371
| | | | | | Attempting to fix lit test failure on ppc. llvm-svn: 275676
* [AVX512] Remove CodeGenOnly VBROADCAST m_Int instructions. They can be ↵Craig Topper2016-07-161-28/+47
| | | | | | implemented with patterns selecting existing instructions. NFC llvm-svn: 275671
* ARM: Initialize LoadStore passes in TargetMachineMatthias Braun2016-07-163-16/+13
| | | | | | | | | | | | | | Initializing them in LLVMInitializeARMTarget() makes them visible early enough for "llc -run-pass usage". This required the pass to be renamed from "arm-load-store-opt" to "arm-ldst-opt", because there already exists an arm-load-store-opt cl::opt switch which would now clash with the passname getting added as a switch in opt. On the bright side the pass name now matches the DEBUG_TYPE name. Renamed "arm-prera-load-store-opt" to "arm-repra-ldst-opt" as well for consistency. llvm-svn: 275661
* MIParser: reject subregister indexes on physregsMatthias Braun2016-07-161-0/+2
| | | | llvm-svn: 275658
* [libFuzzer] add hooks for strstr, strcasestr, strcasecmp, strncasecmpKostya Serebryany2016-07-159-6/+67
| | | | llvm-svn: 275648
* Reapply "Mips: Avoid implicit iterator conversions, NFC"Duncan P. N. Exon Smith2016-07-156-57/+51
| | | | | | | | | | This reverts commit r275562, effectively reapplying r275141. Doug Gilmore reported that there was an error when bisecting the Mips buildbot failure, and that r275141 was not to blame after all. Here is the green build: https://dmz-portal.mips.com/bb/builders/LLVM%20with%20integrated%20assembler%20and%20fPIC%20and%20-O0/builds/803 llvm-svn: 275643
* Minor code cleanups. NFC.Junmo Park2016-07-151-2/+2
| | | | llvm-svn: 275637
* [lanai] Small cleanup: remove/comment out unused argsJacques Pienaar2016-07-1524-94/+97
| | | | llvm-svn: 275636
* AMDGPU: Fix verifier error from partially undef copyMatt Arsenault2016-07-151-5/+3
| | | | | | | | | | | | | | In this situation: %VGPR2<def> = BUFFER_LOAD_DWORD_OFFSET %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR7<def,tied3> = V_MAC_F32_e32 %VGPR0<undef>, %VGPR1<kill>, %VGPR7<kill,tied0>, %EXEC<imp-use> %VGPR3_VGPR4_VGPR5_VGPR6<def> = COPY %VGPR0_VGPR1_VGPR2_VGPR3 %VGPR4<def> = COPY %VGPR2 The copy for VGPR1 -> VGPR4 was an error from reading undefined VGPR1, but VGPR4 is defined immediately after this copy. llvm-svn: 275635
* ExpandPostRAPseudos should transfer implicit uses, not only implicit defsMichael Kuperstein2016-07-151-12/+8
| | | | | | | | | | | | | | | | | | | Previously, we would expand: %BL<def> = COPY %DL<kill>, %EBX<imp-use,kill>, %EBX<imp-def> Into: %BL<def> = MOV8rr %DL<kill>, %EBX<imp-def> Dropping the imp-use on the floor. That confused CriticalAntiDepBreaker, which (correctly) assumes that if an instruction defs but doesn't use a register, that register is dead immediately before the instruction - while in this case, the high lanes of EBX can be very much alive. This fixes PR28560. Differential Revision: https://reviews.llvm.org/D22425 llvm-svn: 275634
* BPF: Use official ELF e_machine valueAlexei Starovoitov2016-07-153-1/+11
| | | | | | | | | The same value for EM_BPF is being propagated to glibc, elfutils, and binutils. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 275633
* [lanai] Fix build by updating calls to getLoad & getStore.Jacques Pienaar2016-07-151-9/+7
| | | | | | rL275592 removed the boolean parameters of SelectionDAG::getLoad and getStore, updating Lanai backend's calls to these functions. llvm-svn: 275631
* [pdb] Teach MsfBuilder and other classes about the Free Page Map.Zachary Turner2016-07-153-8/+16
| | | | | | | | | | | | | | Block 1 and 2 of an MSF file are bit vectors that represent the list of blocks allocated and free in the file. We had been using these blocks to write stream data and other data, so we mark them as the free page map now. We don't yet serialize these pages to the disk, but at least we make a note of what it is, and avoid writing random data to them. Doing this also necessitated cleaning up some of the tests to be more general and hardcode fewer values, which is nice. llvm-svn: 275629
* [pdb] Round trip the NameMap data structure to YAML.Zachary Turner2016-07-153-7/+75
| | | | llvm-svn: 275628
* [pdb] Use MsfBuilder to handle the writing PDBs.Zachary Turner2016-07-159-135/+166
| | | | | | | | | | | | | | | Previously we would read a PDB, then write some of it back out, but write the directory, super block, and other pertinent metadata back out unchanged. This generates incorrect PDBs since the amount of data written was not always the same as the amount of data read. This patch changes things to use the newly introduced `MsfBuilder` class to write out a correct and accurate set of Msf metadata for the data *actually* written, which opens up the door for adding and removing type records, symbol records, and other types of data to an existing PDB. llvm-svn: 275627
* StructurizeCFG: Fix inverting constantexpr conditionsMatt Arsenault2016-07-151-8/+2
| | | | llvm-svn: 275626
* [Hexagon] Handle instruction latency for 0 or 2 cyclesKrzysztof Parzyszek2016-07-155-0/+227
| | | | | | | | | | | | | | | | | | | | | | | The Hexagon schedulers need to handle instructions with a latency of 0 or 2 more accurately. The problem, in v60, is that a dependence between two instructions with a 2 cycle latency can use a .cur version of the source to achieve a 0 cycle latency when the use is in the same packet. Any othe use, must be at least 2 packets later, or a stall occurs. In other words, the compiler does not want to schedule the dependent instructions 1 cycle later. To achieve this, the latency adjustment code allows only a single dependence to have a zero latency. All other instructions have the other value, which is typically 2 cycles. We use a heuristic to determine which instruction gets the 0 latency. The Hexagon machine scheduler was also changed to increase the cost associated with 0 latency dependences than can be scheduled in the same packet. Patch by Brendon Cahoon. llvm-svn: 275625
* AMDGPU: Remove brev intrinsicMatt Arsenault2016-07-152-6/+0
| | | | llvm-svn: 275620
* AMDGPU: Fix TargetPrefix for remaining r600 intrinsicsMatt Arsenault2016-07-153-51/+53
| | | | llvm-svn: 275619
* AMDGPU: Remove AMDGPU.ldexpMatt Arsenault2016-07-151-4/+0
| | | | llvm-svn: 275618
* AMDGPU: Remove legacy rsq.clamped intrinsicMatt Arsenault2016-07-154-15/+7
| | | | | | | | Mesa still has a use of llvm.AMDGPU.rsq.f64 remaining. Also fix mismatch with non-IEEE rsq selecting to IEEE rsq. llvm-svn: 275617
* AMDGPU/R600: Delete dead code.Matt Arsenault2016-07-152-58/+1
| | | | | | Dead or the same as the base implementation. llvm-svn: 275616
* DebugInfo: reorder some initializersSaleem Abdulrasool2016-07-151-2/+2
| | | | | | Fix a few initialization ordering warnings from gcc from `-Wreorder`. NFC. llvm-svn: 275615
* CodeGen: avoid emitting unnecessary CFISaleem Abdulrasool2016-07-151-4/+5
| | | | | | | | | | | | Remove unnecessary clutter in assembly output. When using SjLj EH, the CFI is not actually used for anything. Do not emit the CFI needlessly. The minor test adjustments are interesting. The prologue test was just overzealous matcching. The interesting case is the LSDA change. It was originally added to ensure that various compilations did not mangle the name (it explicitly checked the name!). However, subsequent cleanups made it more reliant on the CFI to find the name. Parse the generated code flow to generically find the label still. llvm-svn: 275614
* Make processInstruction from LCSSA.cpp externally available.Michael Zolotukhin2016-07-151-120/+126
| | | | | | | | | | | | | | | | Summary: When a pass tries to keep LCSSA form it's often convenient to be able to update LCSSA for a set of instructions rather than for the entire loop. This patch makes the processInstruction from LCSSA externally available under a name formLCSSAForInstruction. Reviewers: chandlerc, sanjoy, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22378 llvm-svn: 275613
* [pdb] Introduce MsfBuilder for laying out PDB files.Zachary Turner2016-07-153-0/+290
| | | | | | | Reviewed by: ruiu Differential Revision: https://reviews.llvm.org/D22308 llvm-svn: 275611
* Teach fast isel about the win64 calling convention.Nico Weber2016-07-151-4/+2
| | | | | | | | | | | | | | | This mostly just works. Vectorcall rets are still not supported. The win64_eh test change is because fast isel doesn't use rsi for temporary computations, so it doesn't need to be pushed. The test case I'm changing was originally added to test pushes, but by now there are other test cases in that file exercising that code path. https://reviews.llvm.org/D22422 llvm-svn: 275607
* [Hexagon] Make MI scheduler check for stalls in previous packet on v60Krzysztof Parzyszek2016-07-152-3/+41
| | | | | | Patch by Ikhlas Ajbar. llvm-svn: 275606
* [CFLAA] Add attributes handling for CFLAnders.George Burgess IV2016-07-151-9/+127
| | | | | | | | | | | | This patch adds proper handling of stratified attributes into our anders-style CFLAA implementation. It also comes bundled with more CFLAnders tests. :) Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22325 llvm-svn: 275604
* [PowerPC] Set kill flag for scratch register when spilling the link registerNemanja Ivanovic2016-07-151-1/+1
| | | | | | This fixes PR 28526. llvm-svn: 275603
* [CFLAA] Add an initial CFLAnders implementation.George Burgess IV2016-07-153-27/+464
| | | | | | | | | | | | | This adds an incomplete anders-style implementation for CFLAA. It's incomplete in that it's missing interprocedural analysis, attrs handling, etc. and that it needs more tests. More tests and features will be added in future commits. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22291 llvm-svn: 275602
* Fix calls to SelectionDAG::getStoreDerek Schuff2016-07-151-2/+2
| | | | | | It was refactored in r275592. NFC llvm-svn: 275601
* Revert "[AMDGPU] Add metadata for runtime"Vitaly Buka2016-07-153-371/+0
| | | | | | This reverts commit r275566. llvm-svn: 275599
* [Hexagon] Replace postprocessDAG with a more elaborate DAG mutationKrzysztof Parzyszek2016-07-151-10/+76
| | | | llvm-svn: 275598
* [MBP] Clean up of the comments, and a first attempt to better describe a partSjoerd Meijer2016-07-151-28/+49
| | | | | | | | of the algorithm. Differential Revision: https://reviews.llvm.org/D22364 llvm-svn: 275595
* [SCCP] Merge two conditions into one. NFCI.Davide Italiano2016-07-151-3/+1
| | | | llvm-svn: 275593
* [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, ↵Justin Lebar2016-07-1532-1642/+1192
| | | | | | | | | | | | | | | | | | | | | | | getStore, and friends. Summary: Instead, we take a single flags arg (a bitset). Also add a default 0 alignment, and change the order of arguments so the alignment comes before the flags. This greatly simplifies many callsites, and fixes a bug in AMDGPUISelLowering, wherein the order of the args to getLoad was inverted. It also greatly simplifies the process of adding another flag to getLoad. Reviewers: chandlerc, tstellarAMD Subscribers: jholewinski, arsenm, jyknight, dsanders, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D22249 llvm-svn: 275592
* [CodeGen] Take a MachineMemOperand::Flags in ↵Justin Lebar2016-07-1518-46/+42
| | | | | | | | | | | | | | | | | MachineFunction::getMachineMemOperand. Summary: Previously we took an unsigned. Hooray for type-safety. Reviewers: chandlerc Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D22282 llvm-svn: 275591
* [PGO] IRPGO pre-cleanup pass changesRong Xu2016-07-151-0/+22
| | | | | | | | | | | | | | This patch adds a selected set of cleanup passes including a pre-inline pass before LLVM IR PGO instrumentation. The inline is only intended to apply those obvious/trivial ones before instrumentation so that much less instrumentation is needed to get better profiling information. This will drastically improve the instrumented code performance for large C++ applications. Another benefit is the context sensitive counts that can potentially improve the PGO optimization. Differential Revision: http://reviews.llvm.org/D21405 llvm-svn: 275588
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