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* SLPVectorizer: improved scheduling algorithm.Erik Eckstein2014-08-011-249/+693
| | | | llvm-svn: 214494
* [mips][PR19612] Fix va_arg for big-endian mode.Daniel Sanders2014-08-012-2/+68
| | | | | | | | | | | | | | | | | | Summary: Big-endian mode was not correctly adjusting the offset for types smaller than an ABI slot. Fixes PR19612 Reviewers: dsanders Reviewed By: dsanders Subscribers: sstankovic, llvm-commits Differential Revision: http://reviews.llvm.org/D4556 llvm-svn: 214493
* SLP Vectorizer: added statistics counterErik Eckstein2014-08-011-0/+12
| | | | llvm-svn: 214487
* SLP Vectorizer: improve canonicalize tree operands of commutitive binary ↵Erik Eckstein2014-08-011-28/+41
| | | | | | | | operands. This reverts r214338 (except the test file) and replaces it with a more general algorithm. llvm-svn: 214485
* [PowerPC] Generate unaligned vector loads using intrinsics instead of ↵Hal Finkel2014-08-012-52/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | regular loads Altivec vector loads on PowerPC have an interesting property: They always load from an aligned address (by rounding down the address actually provided if necessary). In order to generate an actual unaligned load, you can generate two load instructions, one with the original address, one offset by one vector length, and use a special permutation to extract the bytes desired. When this was originally implemented, I generated these two loads using regular ISD::LOAD nodes, now marked as aligned. Unfortunately, there is a problem with this: The alignment of a load does not contribute to its identity, and SDNodes are uniqued. So, imagine that we have some unaligned load, L1, that is not aligned. The routine will create two loads, L1(aligned) and (L1+16)(aligned). Further imagine that there had already existed a load (L1+16)(unaligned) with the same chain operand as the load L1. When (L1+16)(aligned) is created as part of the lowering of L1, this load *is* also the (L1+16)(unaligned) node, just now marked as aligned (because the new alignment overwrites the old). But the original users of (L1+16)(unaligned) now get the data intended for the permutation yielding the data for L1, and (L1+16)(unaligned) no longer exists to get its own permutation-based expansion. This was PR19991. A second potential problem has to do with the MMOs on these loads, which can be used by AA during instruction scheduling to break chain-based dependencies. If the new "aligned" loads get the MMO from the original unaligned load, this does not represent the fact that it will load data from below the original address. Normally, this would not matter, but this load might be combined with another load pair for a previous vector, and then the dependency on the otherwise- ignored lower bytes can matter. To fix both problems, instead of generating the necessary loads using regular ISD::LOAD instructions, ppc_altivec_lvx intrinsics are used instead. These are provided with MMOs with a conservative address range. Unfortunately, I no longer have a failing test case (since PR19991 was reported, other changes in CodeGen have forced this bug back into hiding it again). Nevertheless, this should fix the underlying problem. llvm-svn: 214481
* This patch implements transform for pattern "(A & ~B) ^ (~A) -> ~(A & B)".Suyog Sarda2014-08-011-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D4653 llvm-svn: 214479
* This patch implements transform for pattern "(A | B) & ((~A) ^ B) -> (A & B)".Suyog Sarda2014-08-011-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D4628 llvm-svn: 214478
* This patch implements transform for pattern "( A & (~B)) | (A ^ B) -> (A ^ B)"Suyog Sarda2014-08-011-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D4652 llvm-svn: 214477
* This patch implements transform for pattern "(A & B) | ((~A) ^ B) -> (~A ^ B)".Suyog Sarda2014-08-011-0/+10
| | | | | | | | Patch Credit to Ankit Jain ! Differential Revision: http://reviews.llvm.org/D4655 llvm-svn: 214476
* R600/SI: Fix build warningTom Stellard2014-08-011-1/+1
| | | | llvm-svn: 214475
* [FastISel][AArch64] Fix the immediate versions of the ↵Juergen Ributzka2014-08-011-48/+49
| | | | | | | | | | | | {s|u}{add|sub}.with.overflow intrinsics. ADDS and SUBS cannot encode negative immediates or immediates larger than 12bit. This fix checks if the immediate version can be used under this constraints and if we can convert ADDS to SUBS or vice versa to support negative immediates. Also update the test cases to test the immediate versions. llvm-svn: 214470
* [PowerPC] Recognize consecutive memory accesses from intrinsicsHal Finkel2014-08-011-9/+63
| | | | | | | | | | | | | | | When generating unaligned vector loads, we need to search for other loads or stores nearby offset by one vector width. If we find one, then we know that we can safely generate another aligned load at that address. Otherwise, we must generate the next load using an offset of the vector width minus one byte (so we don't read off the end of the allocation if the base unaligned address happened to be aligned at runtime). We had previously done this using only other vector loads and stores, but did not consider the PowerPC-specific vector load/store intrinsics. Now we'll also consider vector intrinsics. By itself, this change is a feature enhancement, but is a necessary step toward fixing the underlying problem behind PR19991. llvm-svn: 214469
* MS inline asm: Fix null SMLoc when 'ptr' is missing after dword & coReid Kleckner2014-08-011-1/+1
| | | | | | | | This improves the diagnostics from the regular assembler, but more importantly it fixes an assertion when parsing inline assembly. Test landing in Clang. llvm-svn: 214468
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-0111-658/+1034
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-012-28/+53
| | | | | | | | | | | | We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. llvm-svn: 214465
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-013-12/+79
| | | | | | | This will prevent us from using extra MOV instructions once we prefer selecting 64-bit instructions. llvm-svn: 214464
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-013-3/+16
| | | | | | | | We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 214463
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-319-68/+110
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* X86 MC: Don't crash on empty memory operand parensReid Kleckner2014-07-311-2/+4
| | | | | | | | Instead, create an absolute memory operand. Fixes PR20504. llvm-svn: 214457
* X86 MC: Reject invalid segment registers before a memory operand colonReid Kleckner2014-07-311-0/+3
| | | | | | Previously we would execute unreachable during object emission. llvm-svn: 214456
* White space fix.Louis Gerbarg2014-07-311-1/+1
| | | | llvm-svn: 214455
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-3118-63/+81
| | | | | | | | | | | | | | Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. llvm-svn: 214449
* Improve the remark generated for -Rpass-missed.Tyler Nowicki2014-07-311-17/+13
| | | | | | | | The current remark is ambiguous and makes it sounds like explicitly specifying vectorization will allow the loop to be vectorized. This is not the case. The improved remark directs the user to -Rpass-analysis=loop-vectorize to determine the cause of the pass-miss. Reviewed by Arnold Schwaighofer` llvm-svn: 214445
* Revert "Remove MCObjectDisassembler.cpp as it is untested and unused." as it ↵Eric Christopher2014-07-312-0/+575
| | | | | | | | is apparently used, but the build didn't return errors weirdly. This reverts commits 214437 and 214438. llvm-svn: 214444
* Improve the remark generated when a variable that is used outside the loop ↵Tyler Nowicki2014-07-311-3/+4
| | | | | | | | is not a reduction or induction variable. Reviewed by Arnold Schwaighofer llvm-svn: 214440
* Fixing CMake problems with MCObjectDisassembler.cpp not existing.Aaron Ballman2014-07-311-1/+0
| | | | llvm-svn: 214438
* Remove MCObjectDisassembler.cpp as it is untested and unused.Eric Christopher2014-07-311-574/+0
| | | | llvm-svn: 214437
* DWOHolder takes ownership of the argument constructor, use std::unique_ptr.Rafael Espindola2014-07-312-5/+6
| | | | | | Thanks to David Blaikie for noticing it. llvm-svn: 214434
* Use a reference instead of a pointer.Rafael Espindola2014-07-314-10/+10
| | | | | | This makes using a std::unique_ptr in the caller more convenient. llvm-svn: 214433
* Disable IsSub subregister assert. pr18663.Will Schmidt2014-07-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up to the activity in the bug at http://llvm.org/bugs/show_bug.cgi?id=18663 . The underlying issue has to do with how the KILL pseudo-instruction is handled. I defer to Hal/Jakob/Uli for additional details and background. This will disable the (bad?) assert, add an associated fixme comment, and add a pair of tests. The code change and the pr18663-2.ll test are copied from the referenced bug. That test does not immediately fail in my environment, but I have added the pr18663.ll test which does. (Comment from Hal) to provide everyone else with some context, this assert was not bad when it was written. At that time, we only generated KILL pseudo instructions around subregister copies. This logic, unfortunately, had its own problems. In r199797, the relevant logic in MachineCopyPropagation was replaced to generate KILLs for other kinds of copies too. This change in semantics broke this now-problematic assumption in AggressiveAntiDepBreaker. The AggressiveAntiDepBreaker really needs a proper cleanup to deal with the change, but removing the assert (which just allows the function to return false) is a safe conservative behavior, and should do for the time being. llvm-svn: 214429
* Move MCObjectSymbolizer.h to MC/MCAnalysis.Rafael Espindola2014-07-312-2/+2
| | | | | | The cpp file is already in lib/MC/MCAnalysis. llvm-svn: 214424
* Fix ScalarEvolutionExpander when creating a PHI in a block with duplicate ↵Hal Finkel2014-07-311-1/+5
| | | | | | | | | | | | | | predecessors It seems that when I fixed this, almost exactly a year ago, I did not quite do it correctly. When we have duplicate block predecessors, we can indeed not have different incoming values for the same block, but we *must* have duplicate entries. So, instead of skipping the duplicates, we explicitly add the duplicate incoming values. Fixes PR20442. llvm-svn: 214423
* UseListOrder: Handle self-usersDuncan P. N. Exon Smith2014-07-311-3/+3
| | | | | | | | | | Correctly sort self-users (such as PHI nodes). I added a targeted test in `test/Bitcode/use-list-order.ll` and the final missing RUN line to tests in `test/Assembly`. This is part of PR5680. llvm-svn: 214417
* Fix loop end condition.Eric Christopher2014-07-311-1/+1
| | | | | Note: This code appears to be untested. llvm-svn: 214416
* Fixing an -Woverloaded-virtual warnings by exposing the hidden virtual ↵Aaron Ballman2014-07-311-0/+1
| | | | | | function as well. No functional changes intended. llvm-svn: 214400
* Fixing a -Wcast-qual warning in GCC. No functional changes.Aaron Ballman2014-07-311-2/+2
| | | | llvm-svn: 214399
* [msan] Fix handling of array types.Evgeniy Stepanov2014-07-311-5/+16
| | | | | | | | Switch array type shadow from a single integer to an array of integers (i.e. make it per-element). This simplifies instrumentation of extractvalue and fixes PR20493. llvm-svn: 214398
* [asan] Support x86 REP MOVS asm instrumentation.Evgeniy Stepanov2014-07-313-20/+153
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 214395
* MergeFunctions, tiny refactoring:Stepan Dyatkovskiy2014-07-311-4/+4
| | | | | | cmpOperation has been renamed to cmpOperations (multiple form). llvm-svn: 214392
* [FastISel][AArch64] Add basic bitcast support for conversion between float ↵Juergen Ributzka2014-07-311-0/+37
| | | | | | | | and int. Fixes <rdar://problem/17867078>. llvm-svn: 214389
* [FastISel][AArch64] Add sqrt intrinsic support.Juergen Ributzka2014-07-311-0/+19
| | | | | | Fixes <rdar://problem/17867067>. llvm-svn: 214388
* InstCombine: Correctly propagate NSW/NUW for x-(-A) -> x+ADavid Majnemer2014-07-311-3/+9
| | | | | | | | | | | | We can only propagate the nsw bits if both subtraction instructions are marked with the appropriate bit. N.B. We only propagate the nsw bit in InstCombine because the nuw case is already handled in InstSimplify. This fixes PR20189. llvm-svn: 214385
* InstSimplify: Simplify (X - (0 - Y)) if the second sub is NUWDavid Majnemer2014-07-311-0/+12
| | | | | | | | | | | If the NUW bit is set for 0 - Y, we know that all values for Y other than 0 would produce a poison value. This allows us to replace (0 - Y) with 0 in the expression (X - (0 - Y)) which will ultimately leave us with X. This partially fixes PR20189. llvm-svn: 214384
* [FastISel][AArch64] Add MachO large code model support for function calls.Juergen Ributzka2014-07-311-10/+105
| | | | | | | | | Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
* A std::unique_ptr case I missed in the previous patch.Rafael Espindola2014-07-312-4/+6
| | | | llvm-svn: 214379
* Use std::unique_ptr to make the ownership explicit.Rafael Espindola2014-07-3110-19/+24
| | | | llvm-svn: 214377
* Don't fail tablegen immediately after failing to set a value.Pete Cooper2014-07-311-1/+4
| | | | | | | | Instead allow the variable to be declared, but don't attach an initializer. This allows more than a single error to be emitted before we exit. Test case to follow soon in another patch. llvm-svn: 214375
* Add a better error message when failing to assign one tablegen value to anotherPete Cooper2014-07-311-1/+8
| | | | | | | | This is currently for assigning from one bit init to another. It can easily be extended to other types. Test to follow soon in another patch. llvm-svn: 214374
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214373
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214372
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