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* [SCEV] Support SCEVUMinExpr in getRangeRef.Florian Hahn2019-09-121-0/+8
| | | | | | | | | | | | | This patch adds support for SCEVUMinExpr to getRangeRef, similar to the support for SCEVUMaxExpr. Reviewers: sanjoy.google, efriedma, reames, nikic Reviewed By: sanjoy.google Differential Revision: https://reviews.llvm.org/D67177 llvm-svn: 371768
* AMDGPU: Fix bug in r371671 on some builds.Austin Kerbow2019-09-121-2/+5
| | | | llvm-svn: 371761
* [LICM/AST] Check if the AliasAny set is removed from the tracker.Alina Sbirlea2019-09-121-2/+10
| | | | | | | | | | | | | | | | Summary: Resolves PR38513. Credit to @bjope for debugging this. Reviewers: hfinkel, uabelho, bjope Subscribers: sanjoy.google, bjope, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67417 llvm-svn: 371752
* [MemorySSA] Pass (for update) MSSAU when hoisting instructions.Alina Sbirlea2019-09-121-19/+28
| | | | | | | | | | | | | | Summary: Pass MSSAU to makeLoopInvariant in order to properly update MSSA. Reviewers: george.burgess.iv Subscribers: Prazek, sanjoy.google, uabelho, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67470 llvm-svn: 371748
* [LV] Support invariant addresses in speculation logicPhilip Reames2019-09-121-10/+18
| | | | | | | | | | Implement a TODO from rL371452, and handle loop invariant addresses in predicated blocks. If we can prove that the load is safe to speculate into the header, then we can avoid using a masked.load in favour of a normal load. This is mostly about vectorization robustness. In the common case, it's generally expected that LICM/LoadStorePromotion would have eliminated such loads entirely. Differential Revision: https://reviews.llvm.org/D67372 llvm-svn: 371745
* [CGP] Ensure sinking multiple instructions does not invalidate dominance checksDavid Green2019-09-121-9/+23
| | | | | | | | | | | | | | | | | | In MVE, as of rL371218, we are attempting to sink chains of instructions such as: %l1 = insertelement <8 x i8> undef, i8 %l0, i32 0 %broadcast.splat26 = shufflevector <8 x i8> %l1, <8 x i8> undef, <8 x i32> zeroinitializer In certain situations though, we can end up breaking the dominance relations of instructions. This happens when we sink the instruction into a loop, but cannot remove the originals. The Use is updated, which might in fact be a Use from the second instruction to the first. This attempts to fix that by reversing the order of instruction that are sunk, and ensuring that we update the uses on new instructions if they have already been sunk, not the old ones. Differential Revision: https://reviews.llvm.org/D67366 llvm-svn: 371743
* [Alignment] Move OffsetToAlignment to Alignment.hGuillaume Chatelet2019-09-1213-41/+54
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, JDevlieghere, alexshap, rupprecht, jhenderson Subscribers: sdardis, nemanjai, hiraditya, kbarton, jakehehrlich, jrtc27, MaskRay, atanasyan, jsji, seiya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67499 llvm-svn: 371742
* [ConstProp] allow folding for fma that produces NaNSanjay Patel2019-09-121-7/+3
| | | | | | | | | | | | | | | | | | | | Folding for fma/fmuladd was added here: rL202914 ...and as seen in existing/unchanged tests, that works to propagate NaN if it's already an input, but we should fold an fma() that creates NaN too. From IEEE-754-2008 7.2 "Invalid Operation", there are 2 clauses that apply to fma, so I added tests for those patterns: c) fusedMultiplyAdd: fusedMultiplyAdd(0, ∞, c) or fusedMultiplyAdd(∞, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled d) addition or subtraction or fusedMultiplyAdd: magnitude subtraction of infinities, such as: addition(+∞, −∞) Differential Revision: https://reviews.llvm.org/D67446 llvm-svn: 371735
* [MIPS GlobalISel] Select indirect branchPetar Avramovic2019-09-123-0/+9
| | | | | | | | Select G_BRINDIRECT for MIPS32. Differential Revision: https://reviews.llvm.org/D67441 llvm-svn: 371730
* [MIPS GlobalISel] Lower G_DYN_STACKALLOCPetar Avramovic2019-09-121-0/+3
| | | | | | | | | | IRTranslator creates G_DYN_STACKALLOC instruction during expansion of alloca when argument that tells number of elements to allocate on stack is a virtual register. Use default lowering for MIPS32. Differential Revision: https://reviews.llvm.org/D67440 llvm-svn: 371728
* [MIPS GlobalISel] Select G_IMPLICIT_DEFPetar Avramovic2019-09-123-1/+39
| | | | | | | | | | G_IMPLICIT_DEF is used for both integer and floating point implicit-def. Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo. Select G_IMPLICIT_DEF for MIPS32. Differential Revision: https://reviews.llvm.org/D67439 llvm-svn: 371727
* [DAGCombine] visitFDIV - Use isCheaperToUseNegatedFPOps helper for (fdiv ↵Simon Pilgrim2019-09-121-15/+5
| | | | | | | | (fneg X), (fneg Y)) -> (fdiv X, Y). NFCI. Minor cleanup to use equivalent helper code. llvm-svn: 371724
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-1229-82/+379
| | | | | | | | This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
* CodeGenPrep: add separate hook say when GEPs should be used for sinking. NFCI.Tim Northover2019-09-121-2/+2
| | | | | | | | | Up to now, we've decided whether to sink address calculations using GEPs or normal arithmetic based on the useAA hook, but there are other reasons GEPs might be preferred. So this patch splits the two questions, with a default implementation falling back to useAA. llvm-svn: 371721
* [InstSimplify] simplifyUnsignedRangeCheck(): handle more cases (PR43251)Roman Lebedev2019-09-121-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I don't have a direct motivational case for this, but it would be good to have this for completeness/symmetry. This pattern is basically the motivational pattern from https://bugs.llvm.org/show_bug.cgi?id=43251 but with different predicate that requires that the offset is non-zero. The completeness bit comes from the fact that a similar pattern (offset != zero) will be needed for https://bugs.llvm.org/show_bug.cgi?id=43259, so it'd seem to be good to not overlook very similar patterns.. Proofs: https://rise4fun.com/Alive/21b Also, there is something odd with `isKnownNonZero()`, if the non-zero knowledge was specified as an assumption, it didn't pick it up (PR43267) Reviewers: spatel, nikic, xbolva00 Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67411 llvm-svn: 371718
* [DAGCombiner] Improve division estimation of floating points.Qiu Chaofan2019-09-121-11/+33
| | | | | | | | | | | | | Current implementation of estimating divisions loses precision since it estimates reciprocal first and does multiplication. This patch is to re-order arithmetic operations in the last iteration in DAGCombiner to improve the accuracy. Reviewed By: Sanjay Patel, Jinsong Ji Differential Revision: https://reviews.llvm.org/D66050 llvm-svn: 371713
* [LegalizeTypes] Remove code for softening a float type to itself.Craig Topper2019-09-125-266/+58
| | | | | | | | | This was previously used to turn fp128 operations into libcalls on X86. This is now done through op legalization after r371672. This restores much of this code to before r254653. llvm-svn: 371709
* Make SwitchInstProfUpdateWrapper strict permanentlyYevgeny Rouban2019-09-121-29/+12
| | | | | | | | | | | | | | | | | | | We have been using -switch-inst-prof-update-wrapper-strict set to true by default for some time. It is time to remove the safety stuff and make SwitchInstProfUpdateWrapper intolerant to inconsistencies in !prof branch_weights metadata of SwitchInst. This patch gets rid of the Invalid state of SwitchInstProfUpdateWrapper and the option -switch-inst-prof-update-wrapper-strict. So there is only two states: changed and unchanged. Reviewers: davidx, nikic, eraman, reames, chandlerc Reviewed By: davidx Differential Revision: https://reviews.llvm.org/D67435 llvm-svn: 371707
* [X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and ↵Craig Topper2019-09-111-0/+2
| | | | | | | | | | | | | | | | later Intel CPUs. AVX512 instructions can cause a frequency drop on these CPUs. This can negate the performance gains from using wider vectors. Enabling prefer-vector-width=256 will prevent generation of zmm registers unless explicit 512 bit operations are used in the original source code. I believe gcc and icc both do something similar to this by default. Differential Revision: https://reviews.llvm.org/D67259 llvm-svn: 371694
* [AArch64][GlobalISel] Fall back on attempts to allocate split types on the ↵Amara Emerson2019-09-111-6/+14
| | | | | | | | | | | | | | | stack. First we were asserting that the ValNo of a VA was the wrong value. It doesn't actually make a difference for us in CallLowering but fix that anyway to silence the assert. The bigger issue was that after fixing the assert we were generating invalid MIR because the merging/unmerging of values split across multiple registers wasn't also implemented for memory locs. This happens when we run out of registers and have to pass the split types like i128 -> i64 x 2 on the stack. This is do-able, but for now just fall back. llvm-svn: 371693
* [GlobalISel][AArch64] Check caller for swifterror params in tailcall eligibilityJessica Paquette2019-09-111-3/+7
| | | | | | | | | | | | | | | | Before, we only checked the callee for swifterror. However, we should also be checking the caller to see if it has a swifterror parameter. Since we don't currently handle outgoing arguments, this didn't show up in the swifterror.ll testcase. Also, remove the swifterror checks from call-translator-tail-call.ll, since they are covered by the existing swifterror testing. Better to have it all in one place. Differential Revision: https://reviews.llvm.org/D67465 llvm-svn: 371692
* [TableGen] Skip CRLF conversion when writing outputReid Kleckner2019-09-111-2/+2
| | | | | | | | | Doing the CRLF translation while writing the file defeats our optimization to not update the file if it hasn't changed. Fixes PR43271. llvm-svn: 371683
* [InstCombine] rename variable for readability; NFCSanjay Patel2019-09-111-21/+21
| | | | | | | There's more that can be done here, but "OpI" doesn't convey that we casted to BinaryOperator. llvm-svn: 371682
* Add some missing changes to GSYM that was addressing a gcc compilation error ↵David Blaikie2019-09-111-1/+1
| | | | | | due to a type and variable with the same name llvm-svn: 371681
* [X86] Fix latent bugs in 32-bit CMPXCHG8B inserterReid Kleckner2019-09-112-7/+11
| | | | | | | | | | | | | | | I found three issues: 1. the loop over E[ABCD]X copies run over BB start 2. the direct address of cmpxchg8b could be a frame index 3. the displacement of cmpxchg8b could be a global instead of an immediate These were all introduced together in r287875, and should be fixed with this change. Issue reported by Zachary Turner. llvm-svn: 371678
* [ConstantFolding] Refactor math functions to use LLVM ones (NFC)Evandro Menezes2019-09-111-37/+42
| | | | | | | | | When possible, replace calls to library routines on the host with equivalent ones in LLVM. Differential revision: https://reviews.llvm.org/D67459 llvm-svn: 371677
* Revert [llvm-nm] Add tapi file supportCyndy Ishida2019-09-113-23/+6
| | | | | | This reverts r371576 (git commit f88f46358dbffa20af3b054a9346e5154789d50f) llvm-svn: 371676
* [X86] Move x86_64 fp128 conversion to libcalls from type legalization to DAG ↵Craig Topper2019-09-112-20/+157
| | | | | | | | | | | | | | legalization fp128 is considered a legal type for a register, but has almost no legal operations so everything needs to be converted to a libcall. Previously this was implemented by tricking type legalization into softening the operations with various checks for "is legal in hardware register" to change the behavior to still use f128 as the resulting type instead of converting to i128. This patch abandons this approach and instead moves the libcall conversions to LegalizeDAG. This is the approach taken by AArch64 where they also have a legal fp128 type, but no legal operations. I think this is more in spirit with how SelectionDAG's phases are supposed to work. I had to make some hacks for STRICT_FP_ROUND because some of the strict FP handling checks if ISD::FP_ROUND is Legal for a given result type, but I had to make ISD::FP_ROUND Custom to allow making a libcall when the input is f128. For all other types the Custom handler just returns the original node. These hacks are incomplete and don't work for a strict truncate from f128, but I don't think it worked before either since LegalizeFloatTypes doesn't know about strict ops yet. I've also raised PR43209 against AArch64 which currently crashes on a strict ftrunc from f64->f32 because of FP_ROUND being marked Custom for the same reason there. Differential Revision: https://reviews.llvm.org/D67128 llvm-svn: 371672
* AMDGPU: Move m0 initializations earlierAustin Kerbow2019-09-111-4/+38
| | | | | | | | | | | | | | | | | Summary: After hoisting and merging m0 initializations schedule them as early as possible in the MBB. This helps the scheduler avoid hazards in some cases. Reviewers: rampitec, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67450 llvm-svn: 371671
* [DWARF] Emit call site parameter info when tuning for lldbVedant Kumar2019-09-111-2/+2
| | | | | | | | | Emit debug entry values using standard DWARF5 opcodes when the debugger tuning is set to lldb. Differential Revision: https://reviews.llvm.org/D67410 llvm-svn: 371666
* Add a LineTable class to GSYM and test it.Greg Clayton2019-09-113-4/+289
| | | | | | | | | | This patch adds the ability to create a gsym::LineTable object, populate it, encode and decode it and test all functionality. The full format of the LineTable encoding is specified in the header file LineTable.h. Differential Revision: https://reviews.llvm.org/D66602 llvm-svn: 371657
* [AMDGPU] Fix crash in phi-elimination hook.Michael Liao2019-09-111-2/+4
| | | | | | | | | | | | | | Summary: - Pre-check in case there's just a single PHI insn. Reviewers: alex-t, rampitec, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl Tags: #llvm Differential Revision: https://reviews.llvm.org/D67451 llvm-svn: 371649
* [ConstantHoisting] Fix non-determinism.Eli Friedman2019-09-111-12/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D66114 llvm-svn: 371644
* [IRMover] Don't map globals if their types are the samePirama Arumuga Nainar2019-09-111-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: During IR Linking, if the types of two globals in destination and source modules are the same, it can only be because the global in the destination module is originally from the source module and got added to the destination module from a shared metadata. We shouldn't map this type to itself in case the type's components get remapped to a new type from the destination (for instance, during the loop over SrcM->getIdentifiedStructTypes() further below in IRLinker::computeTypeMapping()). Fixes PR40312. Reviewers: tejohnson, pcc, srhines Subscribers: mehdi_amini, hiraditya, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66814 llvm-svn: 371643
* LiveIntervals: Split live intervals on multiple dead defsMatt Arsenault2019-09-111-1/+11
| | | | | | | | If there are multiple dead defs of the same virtual register, these are required to be split into multiple virtual registers with separate live intervals to avoid a verifier error. llvm-svn: 371640
* Reland "clang-misexpect: Profile Guided Validation of Performance ↵Petr Hosek2019-09-117-8/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Annotations in LLVM" This patch contains the basic functionality for reporting potentially incorrect usage of __builtin_expect() by comparing the developer's annotation against a collected PGO profile. A more detailed proposal and discussion appears on the CFE-dev mailing list (http://lists.llvm.org/pipermail/cfe-dev/2019-July/062971.html) and a prototype of the initial frontend changes appear here in D65300 We revised the work in D65300 by moving the misexpect check into the LLVM backend, and adding support for IR and sampling based profiles, in addition to frontend instrumentation. We add new misexpect metadata tags to those instructions directly influenced by the llvm.expect intrinsic (branch, switch, and select) when lowering the intrinsics. The misexpect metadata contains information about the expected target of the intrinsic so that we can check against the correct PGO counter when emitting diagnostics, and the compiler's values for the LikelyBranchWeight and UnlikelyBranchWeight. We use these branch weight values to determine when to emit the diagnostic to the user. A future patch should address the comment at the top of LowerExpectIntrisic.cpp to hoist the LikelyBranchWeight and UnlikelyBranchWeight values into a shared space that can be accessed outside of the LowerExpectIntrinsic pass. Once that is done, the misexpect metadata can be updated to be smaller. In the long term, it is possible to reconstruct portions of the misexpect metadata from the existing profile data. However, we have avoided this to keep the code simple, and because some kind of metadata tag will be required to identify which branch/switch/select instructions are influenced by the use of llvm.expect Patch By: paulkirth Differential Revision: https://reviews.llvm.org/D66324 llvm-svn: 371635
* Revert [InstCombine] Use SimplifyFMulInst to simplify multiply in fma.Florian Hahn2019-09-111-5/+3
| | | | | | | | This introduces additional rounding error in some cases. See D67434. This reverts r371518 (git commit 18a1f0818b659cee13865b4fad2648d85984a4ed) llvm-svn: 371634
* [InstSimplify] Pass SimplifyQuery into simplifyUnsignedRangeCheck() and use ↵Roman Lebedev2019-09-111-17/+15
| | | | | | | | | | it for isKnownNonZero() This was actually the original intention in D67332, but i messed up and forgot about it. This patch was originally part of D67411, but precommitting this. llvm-svn: 371630
* LLVM: Optimization Pass: Remove conflicting attribute, if any, beforeWhitney Tsang2019-09-111-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adding new read attribute to an argument Summary: Update optimization pass to prevent adding read-attribute to an argument without removing its conflicting attribute. A read attribute, based on the result of the attribute deduction process, might be added to an argument. The attribute might be in conflict with other read/write attribute currently associated with the argument. To ensure the compatibility of attributes, conflicting attribute, if any, must be removed before a new one is added. The following snippet shows the current behavior of the compiler, where the compilation process is aborted due to incompatible attributes. $ cat x.ll ; ModuleID = 'x.bc' %_type_of_d-ccc = type <{ i8*, i8, i8, i8, i8 }> @d-ccc = internal global %_type_of_d-ccc <{ i8* null, i8 1, i8 13, i8 0, i8 -127 }>, align 8 define void @foo(i32* writeonly %.aaa) { foo_entry: %_param_.aaa = alloca i32*, align 8 store i32* %.aaa, i32** %_param_.aaa, align 8 store i8 0, i8* getelementptr inbounds (%_type_of_d-ccc, %_type_of_d-ccc* @d-ccc, i32 0, i32 3) ret void } $ opt -O3 x.ll Attributes 'readnone and writeonly' are incompatible! void (i32*)* @foo in function foo LLVM ERROR: Broken function found, compilation aborted! The purpose of this changeset is to fix the above error. This fix is based on a suggestion from Johannes @jdoerfert (many thanks!!!) Authored By: anhtuyen Reviewer: nicholas, rnk, chandlerc, jdoerfert Reviewed By: rnk Subscribers: hiraditya, jdoerfert, llvm-commits, anhtuyen, LLVM Tag: LLVM Differential Revision: https://reviews.llvm.org/D58694 llvm-svn: 371622
* [Alignment][NFC] use llvm::Align for AsmPrinter::EmitAlignmentGuillaume Chatelet2019-09-1114-85/+78
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: dschuff, sdardis, nemanjai, hiraditya, kbarton, jrtc27, MaskRay, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67443 llvm-svn: 371616
* [InstCombine] fold sign-bit compares of sremSanjay Patel2019-09-112-0/+44
| | | | | | | | | | | | | | | | | (srem X, pow2C) sgt/slt 0 can be reduced using bit hacks by masking off the sign bit and the module (low) bits: https://rise4fun.com/Alive/jSO A '2' divisor allows slightly more folding: https://rise4fun.com/Alive/tDBM Any chance to remove an 'srem' use is probably worthwhile, but this is limited to the one-use improvement case because doing more may expose other missing folds. That means it does nothing for PR21929 yet: https://bugs.llvm.org/show_bug.cgi?id=21929 Differential Revision: https://reviews.llvm.org/D67334 llvm-svn: 371610
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes ↵Guillaume Chatelet2019-09-1116-40/+40
| | | | | | | | | | | | | | | | | | | | | | mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
* [mips][msa] Fix infinite loop for mips.nori.b intrinsicSimon Atanasyan2019-09-111-0/+1
| | | | | | | | | | | | | | | When value of immediate in `mips.nori.b` is 255 (which has all ones in binary form as 8bit integer) DAGCombiner and Legalizer would fall in an infinite loop. DAGCombiner would try to simplify `or %value, -1` by turning `%value` into UNDEF. Legalizer will turn it back into `Constant<0>` which would then be again turned into UNDEF by DAGCombiner. To avoid this loop we make UNDEF legal for MSA int types on Mips. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D67280 llvm-svn: 371607
* [InstCombine] Fixed handling of isOpNewLike (PR11748)David Bolvansky2019-09-111-7/+8
| | | | llvm-svn: 371602
* [LoopInterchange] Drop unused splitInnerLoopHeader declaration.Florian Hahn2019-09-111-1/+0
| | | | llvm-svn: 371601
* Revert "clang-misexpect: Profile Guided Validation of Performance ↵Dmitri Gribenko2019-09-117-231/+8
| | | | | | | | | | | | | | | | | | | Annotations in LLVM" This reverts commit r371584. It introduced a dependency from compiler-rt to llvm/include/ADT, which is problematic for multiple reasons. One is that it is a novel dependency edge, which needs cross-compliation machinery for llvm/include/ADT (yes, it is true that right now compiler-rt included only header-only libraries, however, if we allow compiler-rt to depend on anything from ADT, other libraries will eventually get used). Secondly, depending on ADT from compiler-rt exposes ADT symbols from compiler-rt, which would cause ODR violations when Clang is built with the profile library. llvm-svn: 371598
* [LoopInterchange] Properly move condition, induction increment and ops to latch.Florian Hahn2019-09-111-11/+50
| | | | | | | | | | | | | | | | | | | | | | | Currently we only rely on the induction increment to come before the condition to ensure the required instructions get moved to the new latch. This patch duplicates and moves the required instructions to the newly created latch. We move the condition to the end of the new block, then process its operands. We stop at operands that are defined outside the loop, or are the induction PHI. We duplicate the instructions and update the uses in the moved instructions, to ensure other users remain intact. See the added test2 for such an example. Reviewers: efriedma, mcrosier Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D67367 llvm-svn: 371595
* [LTO] Avoid calling GlobalValue::getGUID (MD5) twiceFangrui Song2019-09-111-2/+1
| | | | llvm-svn: 371593
* [TLI][AMDGPU] AMDPAL does not have library functionsTim Renouf2019-09-111-12/+2
| | | | | | | | | | | Configure TLI to say that r600/amdgpu does not have any library functions, such that InstCombine does not do anything like turn sin/cos into the library function @tan with sufficient fast math flags. Differential Revision: https://reviews.llvm.org/D67406 Change-Id: I02f907d3e64832117ea9800e9f9285282856e5df llvm-svn: 371592
* [Attributor] Implement "noalias" callsite argument deductionHideto Ueno2019-09-111-4/+50
| | | | | | | | | | | | | | | | Summary: Now, `nocapture` is deduced in Attributor therefore, this patch introduces deduction for `noalias` callsite argument using `nocapture`. Reviewers: jdoerfert, sstefan1 Reviewed By: jdoerfert Subscribers: lebedev.ri, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67286 llvm-svn: 371590
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