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* refactor matches for De Morgan's Laws; NFCISanjay Patel2015-09-081-17/+32
| | | | llvm-svn: 247061
* AMDGPU: Mark s_barrier as a high latency instructionMatt Arsenault2015-09-082-0/+3
| | | | | | | | | | | These were marked as WriteSALU, which is low latency. I'm guessing at the value to use, but it should probably be considered the highest latency instruction. I'm not sure this has any actual effect since hasSideEffects probably is preventing any moving of these. llvm-svn: 247060
* AMDGPU: Fix s_barrier flagsMatt Arsenault2015-09-081-2/+1
| | | | | | | | This should be convergent. This is not a barrier in the isBarrier sense, nor hasCtrlDep. llvm-svn: 247059
* x32. Fixes a bug in i8mem_NOREX declaration.Derek Schuff2015-09-082-6/+17
| | | | | | | | | | | | | | The old implementation assumed LP64 which is broken for x32. Specifically, the MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit physreg copy instruction' error message to be reported. This patch also enable the h-register*ll tests for x32. Differential Revision: http://reviews.llvm.org/D12336 Patch by João Porto llvm-svn: 247058
* AMDGPU: Handle sub of constant for DS offset foldingMatt Arsenault2015-09-081-11/+62
| | | | | | | | | sub C, x - > add (sub 0, x), C for DS offsets. This is mostly to fix regressions that show up when SeparateConstOffsetFromGEP is enabled. llvm-svn: 247054
* Fix PR 24723 - Handle 0-mass backedges in irreducible loopsDiego Novillo2015-09-081-1/+4
| | | | | | | | | | | | This corner case happens when we have an irreducible SCC that is deeply nested. As we work down the tree, the backedge masses start getting smaller and smaller until we reach one that is down to 0. Since we distribute the incoming mass using the backedge masses as weight, the distributor does not allow zero weights. So, we simply ignore them (which will just use the weights of the non-zero nodes). llvm-svn: 247050
* [MC/ELF] Accept zero for .align directiveDavide Italiano2015-09-081-1/+5
| | | | | | | | | | .align directive refuses alignment 0 -- a comment in the code hints this is done for GNU as compatibility, but it seems GNU as accepts .align 0 (and silently rounds up alignment to 1). Differential Revision: http://reviews.llvm.org/D12682 llvm-svn: 247048
* Fix CPP Backend for GEP API changes for opaque pointer typesDavid Blaikie2015-09-081-15/+10
| | | | | | Based on a patch by Jerome Witmann. llvm-svn: 247047
* remove function names from comments; NFCSanjay Patel2015-09-081-49/+45
| | | | llvm-svn: 247043
* Fix for bz24500: Avoid non-deterministic code generation triggered by the ↵Andrew Kaylor2015-09-081-22/+25
| | | | | | | | | | x86 call frame optimization Patch by Dave Kreitzer Differential Revision: http://reviews.llvm.org/D12620 llvm-svn: 247042
* [libFuzzer] better documentatio for -save_minimized_corpus=1Kostya Serebryany2015-09-081-1/+2
| | | | llvm-svn: 247033
* [libFuzzer] remove -iterations as redundant (there is also -num_runs)Kostya Serebryany2015-09-084-7/+4
| | | | llvm-svn: 247030
* WebAssembly: NFC rename shr/sarJF Bastien2015-09-081-2/+2
| | | | | | Renamed from: https://github.com/WebAssembly/design/pull/332 llvm-svn: 247028
* [libFuzzer] add one more mutator: Mutate_ChangeASCIIIntegerKostya Serebryany2015-09-083-0/+67
| | | | llvm-svn: 247027
* Remove white space (test commit)Jun Bum Lim2015-09-081-1/+1
| | | | llvm-svn: 247021
* [mips][microMIPS] Implement LLE, LUI, LW and LWE instructionsZoran Jovanovic2015-09-083-1/+84
| | | | | | Differential Revision: http://reviews.llvm.org/D1179 llvm-svn: 247017
* AVX512: kunpck encoding implementation Igor Breger2015-09-082-17/+17
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D12061 llvm-svn: 247010
* [WebAssembly] Enable SSA lowering and other pre-regalloc passesDan Gohman2015-09-081-1/+21
| | | | llvm-svn: 247008
* Removed an old comment, NFCElena Demikhovsky2015-09-081-2/+0
| | | | llvm-svn: 247006
* [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructionsZoran Jovanovic2015-09-086-2/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
* There is a trunc(lshr (zext A), Cst) optimization in InstCombineCasts thatJakub Kuderski2015-09-081-0/+20
| | | | | | | | | | | removes cast by performing the lshr on smaller types. However, currently there is no trunc(lshr (sext A), Cst) variant. This patch add such optimization by transforming trunc(lshr (sext A), Cst) to ashr A, Cst. Differential Revision: http://reviews.llvm.org/D12520 llvm-svn: 246997
* [mips] Reserve address spaces 1-255 for software use.Daniel Sanders2015-09-081-0/+8
| | | | | | | | | | | | Summary: And define them to have noop casts with address spaces 0-255. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12678 llvm-svn: 246990
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-09-082-2/+4
| | | | | | | | 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions Differential Revision: http://reviews.llvm.org/D10956 llvm-svn: 246987
* compilation issue, NFCElena Demikhovsky2015-09-081-3/+3
| | | | llvm-svn: 246983
* fixed compilation issue, NFC.Elena Demikhovsky2015-09-081-3/+3
| | | | llvm-svn: 246982
* AVX-512: Lowering for 512-bit vector shuffles.Elena Demikhovsky2015-09-084-68/+324
| | | | | | | | Vector types: <8 x 64>, <16 x 32>, <32 x 16> float and integer. Differential Revision: http://reviews.llvm.org/D10683 llvm-svn: 246981
* [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, ↵Zoran Jovanovic2015-09-074-12/+155
| | | | | | | | FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions Differential Revision: http://reviews.llvm.org/D11674 llvm-svn: 246968
* [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructionsZoran Jovanovic2015-09-076-10/+94
| | | | | | Differential Revision: http://reviews.llvm.org/D11181 llvm-svn: 246963
* [ARM] Get rid of SelectT2ShifterOperandReg, NFCJohn Brawn2015-09-072-26/+2
| | | | | | | | | SelectT2ShifterOperandReg has identical behaviour to SelectImmShifterOperand, so get rid of it and use SelectImmShifterOperand instead. Differential Revision: http://reviews.llvm.org/D12195 llvm-svn: 246962
* [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, ↵Zoran Jovanovic2015-09-074-58/+290
| | | | | | | | MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D12141 llvm-svn: 246960
* Prune utf8 chars in comments.NAKAMURA Takumi2015-09-072-3/+3
| | | | llvm-svn: 246953
* [InstCombine] Don't divide by zero when evaluating a potential transformDavid Majnemer2015-09-061-0/+8
| | | | | | | | | | Trivial multiplication by zero may survive the worklist. We tried to reassociate the multiplication with a division instruction, causing us to divide by zero; bail out instead. This fixes PR24726. llvm-svn: 246939
* [SelectionDAG] Swap commutative binops before constant-based foldingHal Finkel2015-09-061-6/+7
| | | | | | | | | | | | | | | | | In searching for a fix for the underlying code-quality bug highlighted by r246937 (that SDAG simplification can lead to us generating an ISD::OR node with a constant zero LHS), I ran across this: We generically canonicalize commutative binary-operation nodes in SDAG getNode so that, if only one operand is a constant, it will be on the RHS. However, we were doing this only after a bunch of constant-based simplification checks that all assume this canonical form (that any constant will be on the RHS). Moving the operand-swapping canonicalization prior to these checks seems like the right thing to do (and, as it turns out, causes SDAG to completely fold away the computation in test/CodeGen/ARM/2012-11-14-subs_carry.ll, just like InstCombine would do). llvm-svn: 246938
* [PowerPC] Don't commute trivial rlwimi instructionsHal Finkel2015-09-061-0/+5
| | | | | | | | | | | | | | | To commute a trivial rlwimi instructions (meaning one with a full mask and zero shift), we'd need to ability to form an all-zero mask (instead of an all-one mask) using rlwimi. We can't represent this, however, and we'll miscompile code if we try. The code quality problem that this highlights (that SDAG simplification can lead to us generating an ISD::OR node with a constant zero LHS) will be fixed as a follow-up. Fixes PR24719. llvm-svn: 246937
* [InstCombine] Don't assume m_Mul gives back an InstructionDavid Majnemer2015-09-051-1/+3
| | | | | | This fixes PR24713. llvm-svn: 246933
* Added arch extensions and default target features in TargetParser.Alexandros Lamprineas2015-09-051-5/+30
| | | | | Differential: http://reviews.llvm.org/D11590 llvm-svn: 246930
* [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, ↵Zoran Jovanovic2015-09-053-4/+159
| | | | | | | | MADDF.fmt, MSUBF.fmt and NEG.fmt instructions Differential Revision: http://reviews.llvm.org/D11978 llvm-svn: 246919
* Fix build warning.Craig Topper2015-09-051-1/+1
| | | | llvm-svn: 246908
* WinCOFFObjectWriter.cpp: Roll back TimeDateStamp along ENABLE_TIMESTAMPS.NAKAMURA Takumi2015-09-051-0/+5
| | | | | | | We want a deterministic output. GNU AS leaves it zero. FIXME: It may be optional by its user, like llc and clang. llvm-svn: 246905
* Fix build warningAndrew Kaylor2015-09-051-2/+2
| | | | llvm-svn: 246903
* [PowerPC] Fix and(or(x, c1), c2) -> rlwimi generationHal Finkel2015-09-051-3/+15
| | | | | | | | | | | | | | | | PPCISelDAGToDAG has a transformation that generates a rlwimi instruction from an input pattern that looks like this: and(or(x, c1), c2) but the associated logic does not work if there are bits that are 1 in c1 but 0 in c2 (these are normally canonicalized away, but that can't happen if the 'or' has other users. Make sure we abort the transformation if such bits are discovered. Fixes PR24704. llvm-svn: 246900
* Fix build warningAndrew Kaylor2015-09-041-4/+0
| | | | llvm-svn: 246899
* [WinEH] Teach SimplfyCFG to eliminate empty cleanup pads.Andrew Kaylor2015-09-041-20/+201
| | | | | | Differential Revision: http://reviews.llvm.org/D12434 llvm-svn: 246896
* [libFuzzer] more accurate logic for traces, 80-char fixKostya Serebryany2015-09-041-6/+5
| | | | llvm-svn: 246888
* Remove two unused includes and C++11 rangify for loops.Yaron Keren2015-09-041-15/+12
| | | | llvm-svn: 246865
* Typo. NFC.Chad Rosier2015-09-041-1/+1
| | | | llvm-svn: 246851
* [MC] Replace comparison with isUInt<32>.David Majnemer2015-09-041-1/+1
| | | | | | | Casting to unsigned long can cause the time to get truncated to 32-bits, making it appear to be a valid timestamp. Just use isUInt<32> instead. llvm-svn: 246840
* WinCOFFObjectWriter.cpp: Appease a warning in checking std::time_t. ↵NAKAMURA Takumi2015-09-041-1/+1
| | | | | | [-Wsign-compare] llvm-svn: 246839
* [libFuzzer] when a single mutation fails try a few more times with other ↵Kostya Serebryany2015-09-041-7/+14
| | | | | | mutations before returning un-mutated data llvm-svn: 246828
* [libFuzzer] actually make the dictionaries work (+docs)Kostya Serebryany2015-09-049-24/+170
| | | | llvm-svn: 246825
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