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* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-122-7/+24
| | | | llvm-svn: 137476
* add two missing function implsChris Lattner2011-08-121-0/+11
| | | | llvm-svn: 137470
* add new accessors to reflect new terminology in struct types.Chris Lattner2011-08-121-2/+44
| | | | llvm-svn: 137468
* Revert r137310 because it does not optimize any code on ToTNadav Rotem2011-08-121-32/+0
| | | | llvm-svn: 137466
* Whitespace and formatting. No functional change intended.Chad Rosier2011-08-121-10/+9
| | | | llvm-svn: 137463
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-1218-14/+29
| | | | | | when building with assertions disabled. llvm-svn: 137460
* MachOWriter: Don't crash on fixups with arithmetic, emit a relocation ↵Benjamin Kramer2011-08-121-2/+6
| | | | | | instead. This matches what as does. llvm-svn: 137414
* findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.Andrew Trick2011-08-121-2/+2
| | | | | | Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it. llvm-svn: 137404
* Don't convert objc_autoreleaseReturnValue to objc_autorelease if the resultDan Gohman2011-08-121-6/+13
| | | | | | is returned through a bitcast. llvm-svn: 137402
* Don't let arbitrary calls disrupt nested retain+release pairs ifDan Gohman2011-08-121-56/+78
| | | | | | | | | the retains and releases all use the same SSA pointer value. Also, don't let CFG hazards disrupt nested retain+release pair optimizations. llvm-svn: 137399
* Use an actual reverse-CFG reverse-postorder for the bottom-up traversal,Dan Gohman2011-08-121-16/+30
| | | | | | | rather than plain postorder, so that CFG constructs like single-exit loops are reliably visited in a sensible order. llvm-svn: 137398
* Simplify the interference checking code a bit.Jakob Stoklund Olesen2011-08-122-112/+42
| | | | | | | This is possible now that we now longer provide an interface to iterate the interference overlaps. llvm-svn: 137397
* ARM vector compare to zero instruction assembly parsing support.Jim Grosbach2011-08-111-0/+15
| | | | llvm-svn: 137389
* Allow loop unrolling to get known trip counts from ScalarEvolution.Andrew Trick2011-08-112-7/+80
| | | | | | | | | | | | | SCEV unrolling can unroll loops with arbitrary induction variables. It is a prerequisite for -disable-iv-rewrite performance. It is also easily handles loops of arbitrary structure including multiple exits and is generally more robust. This is under a temporary option to avoid affecting default behavior for the next couple of weeks. It is needed so that I can checkin unit tests for updateUnloop. llvm-svn: 137384
* Remove the InterferenceResult class.Jakob Stoklund Olesen2011-08-111-32/+0
| | | | llvm-svn: 137381
* Eliminate the last use of InterferenceResult.Jakob Stoklund Olesen2011-08-112-63/+57
| | | | | | | | The Query class now holds two iterators instead of an InterferenceResult instance. The iterators are used as bookmarks for repeated collectInterferingVRegs calls. llvm-svn: 137380
* Enclose directive .cprestore with .set macro and nomacro to silence assemblerAkira Hatanaka2011-08-111-3/+9
| | | | | | warning. llvm-svn: 137378
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Add a dag combine to xform 256-bit shuffles into simple vectorBruno Cardoso Lopes2011-08-111-1/+54
| | | | | | | inserts and extracts. This simple combine makes us generate only 1 instruction instead of 11 in the v8 case. llvm-svn: 137362
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-112-2/+29
| | | | llvm-svn: 137356
* Remove more dead code.Jakob Stoklund Olesen2011-08-112-37/+3
| | | | | | | collectInterferingVRegs will be the primary function for interference checks. llvm-svn: 137354
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-113-18/+60
| | | | llvm-svn: 137353
* Fix typos in comments, and delete an unused function.Dan Gohman2011-08-111-6/+2
| | | | llvm-svn: 137352
* Add isIndirectBranch flag.Akira Hatanaka2011-08-111-1/+2
| | | | llvm-svn: 137351
* Privatize an unused part of the LiveIntervalUnion::Query interface.Jakob Stoklund Olesen2011-08-112-19/+13
| | | | | | No clients are iterating over interference overlaps. llvm-svn: 137350
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Remove some dead code.Jakob Stoklund Olesen2011-08-112-39/+0
| | | | | | | | The InterferenceResult iterator turned out to be less important than we thought it would be. LiveIntervalUnion clients want higher level information, like the list of interfering virtual registers. llvm-svn: 137346
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-112-11/+11
| | | | llvm-svn: 137345
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-111-48/+50
| | | | llvm-svn: 137344
* ARM STRD assembly parsing and encoding.Jim Grosbach2011-08-113-62/+54
| | | | llvm-svn: 137342
* Fix for LoopInfo::updateUnloop. Remove subloop blocks from formerAndrew Trick2011-08-111-16/+29
| | | | | | | | | ancestor loops. I have a unit test that depends on scev-unroll, which unfortunately isn't checked in. But I will check it in when I can. llvm-svn: 137341
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-113-2/+75
| | | | llvm-svn: 137340
* Tidy up.Jim Grosbach2011-08-111-1/+0
| | | | llvm-svn: 137339
* ARM STRBT assembly parsing and encoding.Jim Grosbach2011-08-112-25/+37
| | | | llvm-svn: 137337
* ARM STR(immediate) assembly parsing and encoding.Jim Grosbach2011-08-112-3/+22
| | | | llvm-svn: 137331
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137325
* Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.Bruno Cardoso Lopes2011-08-111-2/+9
| | | | llvm-svn: 137324
* Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson2011-08-112-2/+2
| | | | | | cannot be PC. llvm-svn: 137323
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-112-4/+17
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* Plug a memory leak.Benjamin Kramer2011-08-111-3/+3
| | | | llvm-svn: 137321
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-111-116/+159
| | | | llvm-svn: 137320
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-112-0/+23
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
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