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* more tidying.Chris Lattner2010-07-052-10/+5
| | | | llvm-svn: 107615
* some notes about suboptimal insertps'sChris Lattner2010-07-051-0/+31
| | | | llvm-svn: 107613
* random tidyingChris Lattner2010-07-052-41/+43
| | | | llvm-svn: 107612
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-053-19/+1
| | | | llvm-svn: 107610
* rip out the various v2f32 "mmx" handling logic, now that Chris Lattner2010-07-051-6/+6
| | | | | | v2f32 is illegal on x86. llvm-svn: 107609
* Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.Jakob Stoklund Olesen2010-07-041-0/+2
| | | | llvm-svn: 107602
* Just rip v2f32 support completely out of the X86 backend. InChris Lattner2010-07-041-23/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the example in the testcase, we now generate: _test1: ## @test1 movss 4(%esp), %xmm0 addss 8(%esp), %xmm0 movl 12(%esp), %eax movss %xmm0, (%eax) ret instead of: _test1: ## @test1 subl $20, %esp movl 24(%esp), %eax movq %mm0, (%esp) movq %mm0, 8(%esp) movss (%esp), %xmm0 addss 12(%esp), %xmm0 movss %xmm0, (%eax) addl $20, %esp ret v2f32 support did not work reliably because most of the X86 backend didn't know it was legal. It was apparently only added to support returning source-level v2f32 values in MMX registers in x86-32 mode. If ABI compatibility is important on this GCC-extended-vector type for some reason, then the frontend should generate IR that returns v2i32 instead of v2f32. However, we generally don't try very hard to be abi compatible on gcc extended vectors. llvm-svn: 107601
* fix PR7518 - terrible codegen of <2 x float>, by only markingChris Lattner2010-07-041-6/+16
| | | | | | | | v2f32 as legal in 32-bit mode. It is just as terrible there, but I just care about x86-64 and noone claims it is valuable in 64-bit mode. llvm-svn: 107600
* indentationChris Lattner2010-07-041-2/+3
| | | | llvm-svn: 107599
* Infer alignments of fixed frame objects when they are constructed. This ↵Evan Cheng2010-07-042-18/+7
| | | | | | ensures remat'ed loads from fixed slots have the right alignments. llvm-svn: 107591
* Revert r107583. I no longer think that this is the way to solve the problem.Bill Wendling2010-07-041-2/+2
| | | | llvm-svn: 107585
* Mark sse_load_f32 and sse_load_f64 as having memory operandsBill Wendling2010-07-041-2/+2
| | | | | | | (SDNPMemOperand). This way when they're morphed the memory operands will be copied as well. llvm-svn: 107583
* Proper indentation.Bill Wendling2010-07-041-1/+1
| | | | llvm-svn: 107581
* Minor amendment to switch-lowering improvement.Eli Friedman2010-07-031-2/+10
| | | | llvm-svn: 107569
* Note switch-lowering inefficiency.Eli Friedman2010-07-031-0/+36
| | | | llvm-svn: 107565
* Add AVX SSE4.1 blend, mpsadbw and vdpBruno Cardoso Lopes2010-07-031-0/+19
| | | | llvm-svn: 107560
* Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructionsBruno Cardoso Lopes2010-07-031-0/+26
| | | | llvm-svn: 107558
* Fix typo.Eric Christopher2010-07-031-1/+1
| | | | llvm-svn: 107556
* Add AVX SSE4.1 Horizontal Minimum and Position instructionBruno Cardoso Lopes2010-07-031-0/+3
| | | | llvm-svn: 107552
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-0318-70/+56
| | | | | | slots so it's always false. llvm-svn: 107550
* Add AVX SSE4.1 round instructionsBruno Cardoso Lopes2010-07-031-0/+76
| | | | llvm-svn: 107549
* Detect and handle COPY in many places.Jakob Stoklund Olesen2010-07-039-40/+67
| | | | | | | This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. llvm-svn: 107547
* Simple refactoring of SSE4.1 instructions, making room for the AVX formsBruno Cardoso Lopes2010-07-021-151/+117
| | | | llvm-svn: 107540
* 80-col fixup.Eric Christopher2010-07-021-1/+2
| | | | llvm-svn: 107537
* Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen2010-07-021-0/+49
| | | | | | | | | | | The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. llvm-svn: 107529
* - Add support for the rest of AVX SSE3 instructionsBruno Cardoso Lopes2010-07-022-19/+89
| | | | | | | - Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode llvm-svn: 107523
* Custom inserters (e.g., conditional moves in Thumb1 can introduceJim Grosbach2010-07-021-1/+14
| | | | | | | | | | | | new basic blocks, and if used as a function argument, that can cause call frame setup / destroy pairs to be split across a basic block boundary. That prevents us from doing a simple assertion to check that the pairs match and alloc/ dealloc the same amount of space. Modify the assertion to only check the amount allocated when there are matching pairs in the same basic block. rdar://8022442 llvm-svn: 107517
* MDString is already checked earlier.Devang Patel2010-07-021-1/+1
| | | | llvm-svn: 107516
* Remove early IT block formation. It's not used.Evan Cheng2010-07-023-213/+6
| | | | llvm-svn: 107513
* - Two-address pass should not assume unfolding is always successful.Evan Cheng2010-07-022-12/+27
| | | | | | | | | - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. llvm-svn: 107509
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-026-12/+23
| | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. llvm-svn: 107506
* Remove invalid assertJakob Stoklund Olesen2010-07-021-1/+0
| | | | llvm-svn: 107505
* Properly handle debug values during inline spilling.Jakob Stoklund Olesen2010-07-021-13/+32
| | | | llvm-svn: 107503
* beautify outputGabor Greif2010-07-021-0/+1
| | | | llvm-svn: 107500
* use ArgOperand APIGabor Greif2010-07-021-2/+2
| | | | llvm-svn: 107498
* Don't claim to preserve AliasAnalysis. First, this is doesn't actuallyDan Gohman2010-07-021-1/+0
| | | | | | | have any effect, and second, deleting stores can potentially invalidate an AliasAnalysis, and there's currently no notification for this. llvm-svn: 107496
* Rematerialize as much as possible before inserting spills and reloads.Jakob Stoklund Olesen2010-07-021-60/+179
| | | | | | | | | | This allows us to recognize the common case where all uses could be rematerialized, and no stack slot allocation is necessary. If some values could be fully rematerialized, remove them from the live range before allocating a stack slot for the rest. llvm-svn: 107492
* 80-column and trailing whitespace cleanup.Jim Grosbach2010-07-021-28/+33
| | | | llvm-svn: 107490
* grammar tweaksJim Grosbach2010-07-021-3/+3
| | | | llvm-svn: 107489
* Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson2010-07-022-4/+4
| | | | | | | that it checks the immediate values, not just the instructions opcodes. Radar 8110263. llvm-svn: 107487
* use ArgOperand API (found by my previous commit)Gabor Greif2010-07-021-6/+6
| | | | llvm-svn: 107482
* IndirectBr is not safe to speculatively execute (!)Dan Gohman2010-07-021-0/+1
| | | | llvm-svn: 107454
* Rename CreateReg to CreateRegs, and MakeReg to CreateReg.Dan Gohman2010-07-025-14/+15
| | | | llvm-svn: 107451
* Shrink down SSE3 code by more multiclass refactoringBruno Cardoso Lopes2010-07-011-149/+99
| | | | llvm-svn: 107448
* Make the "linker_private" linkage type emit a non-weak symbol to the file. ItBill Wendling2010-07-011-1/+1
| | | | | | will still be stripped by the linker when it generates the final image. llvm-svn: 107440
* Shrink down SSE3 code by some multiclass refactoring - 1st partBruno Cardoso Lopes2010-07-011-74/+17
| | | | llvm-svn: 107438
* ARM function alignments were off by a power of two. svn 83242 changedBob Wilson2010-07-011-1/+1
| | | | | | | | | getFunctionAlignment and the corresponding use of that value in the ARM asm printer, but now we're using the standard asm printer. The result of this was that function alignments were dropped completely for Thumb functions. Radar 8143571. llvm-svn: 107435
* Implement the "linker_private_weak" linkage type. This will be used forBill Wendling2010-07-0112-19/+41
| | | | | | | | | | | | | | | | | | | | | | | Objective-C metadata types which should be marked as "weak", but which the linker will remove upon final linkage. However, this linkage isn't specific to Objective-C. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". Currently only supported on Darwin platforms. llvm-svn: 107433
* Do not require line number entry for undefined local variable.Devang Patel2010-07-011-2/+4
| | | | | | This is a regression caused by r106792 and caught by gdb testsuite. llvm-svn: 107430
* MC: Fix some stray hunks I didn't intend to commit.Daniel Dunbar2010-07-011-1/+2
| | | | llvm-svn: 107428
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