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* Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin2012-06-051-2/+2
| | | | llvm-svn: 158013
* LoopUnroll: always check for NULL LoopPassManagerAndrew Trick2012-06-051-3/+5
| | | | llvm-svn: 158007
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
| | | | llvm-svn: 158004
* X86 itinerary properties.Andrew Trick2012-06-052-2/+29
| | | | llvm-svn: 157981
* ARM itinerary properties.Andrew Trick2012-06-053-22/+10
| | | | llvm-svn: 157980
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-058-22/+22
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. llvm-svn: 157979
* sdsched: Use the right heuristics when -mcpu is not provided and we have no ↵Andrew Trick2012-06-051-13/+12
| | | | | | | | itinerary. Use ILP heuristics for long latency instrs if no scoreboard exists. llvm-svn: 157978
* misched: Allow disabling scoreboard hazard checking for subtargets with aAndrew Trick2012-06-051-6/+12
| | | | | | | | valid itinerary but no pipeline stages. An itinerary can contain useful scheduling information without specifying pipeline stages for each instruction. llvm-svn: 157977
* whitespaceAndrew Trick2012-06-052-5/+2
| | | | llvm-svn: 157976
* misched: comments from code review.Andrew Trick2012-06-051-3/+3
| | | | llvm-svn: 157975
* Remove the last remat-related code from LiveIntervalAnalysis.Jakob Stoklund Olesen2012-06-051-95/+0
| | | | | | Rematerialization is handled by LiveRangeEdit now. llvm-svn: 157974
* Stop using LiveIntervals::isReMaterializable().Jakob Stoklund Olesen2012-06-051-9/+24
| | | | | | | | | | It is an old function that does a lot more than required by CalcSpillWeights, which was the only remaining caller. The isRematerializable() function never actually sets the isLoad argument, so don't try to compute that. llvm-svn: 157973
* Revert commit r157966Joel Jones2012-06-051-24/+0
| | | | llvm-svn: 157972
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+24
| | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> llvm-svn: 157966
* Delete dead code.Jakob Stoklund Olesen2012-06-041-8/+0
| | | | llvm-svn: 157963
* When gvn decides to replace an instruction with another, we have to patch theRafael Espindola2012-06-041-2/+200
| | | | | | | | | | | | replacement to make it at least as generic as the instruction being replaced. This includes: * dropping nsw/nuw flags * getting the least restrictive tbaa and fpmath metadata * merging ranges Fixes PR12979. llvm-svn: 157958
* Switch LiveIntervals member variable to LLVM naming standards.Jakob Stoklund Olesen2012-06-041-57/+57
| | | | | | No functional change. llvm-svn: 157957
* Pass context pointers to LiveRangeCalc::reset().Jakob Stoklund Olesen2012-06-043-55/+45
| | | | | | | Remove the same pointers from all the other LiveRangeCalc functions, simplifying the interface. llvm-svn: 157941
* Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node isAkira Hatanaka2012-06-041-1/+2
| | | | | | inserted after the shift-left-logical node. llvm-svn: 157937
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-047-11/+71
| | | | llvm-svn: 157935
* MIPS TLS: use the model selected by TargetMachine::getTLSModel().Hans Wennborg2012-06-041-3/+4
| | | | | | This was mostly done already in r156162, but I missed one place. llvm-svn: 157929
* Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem2012-06-041-12/+1
| | | | llvm-svn: 157925
* Better comments for TLS-related X86 MachineOperand flags.Hans Wennborg2012-06-041-9/+18
| | | | llvm-svn: 157920
* Add intrinsic forms for FMA instructions to opcode folding tables.Craig Topper2012-06-042-109/+141
| | | | llvm-svn: 157917
* Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 ↵Craig Topper2012-06-041-0/+34
| | | | | | forms of scalar FMA instructions. llvm-svn: 157914
* Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no ↵Hal Finkel2012-06-042-42/+0
| | | | | | functionality change). llvm-svn: 157912
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-041-5/+3
| | | | | | | It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. llvm-svn: 157911
* Represent .rept as an anonymous macro. This removes the need for the ActiveReptRafael Espindola2012-06-031-55/+88
| | | | | | | vector. No functionality change. Extracted from a patch by the PaX Team. llvm-svn: 157909
* Add a typedef to simplify the code a bit. Not functionality change.Rafael Espindola2012-06-031-7/+9
| | | | | | Part of a patch by the PaX Team. llvm-svn: 157908
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-035-10/+10
| | | | llvm-svn: 157903
* Simplify the fma4 renaming code.Craig Topper2012-06-031-71/+3
| | | | llvm-svn: 157902
* Autoupgrade support the rename of x86.fma4 intrinsics to x86.fma from r157898.Craig Topper2012-06-031-0/+74
| | | | llvm-svn: 157899
* Rename fma4 intrinsics to just fma since they are now used for both FMA4 and ↵Craig Topper2012-06-031-54/+54
| | | | | | FMA3. Autoupgrade support coming in a separate commit. llvm-svn: 157898
* Revert r157831Manman Ren2012-06-033-331/+0
| | | | llvm-svn: 157896
* Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit ↵Craig Topper2012-06-031-36/+30
| | | | | | loads to match instruction behavior. llvm-svn: 157895
* Add neverHasSideEffects and mayLoad to FMA3 instructions.Craig Topper2012-06-031-0/+5
| | | | llvm-svn: 157894
* Use access(2) instead of stat(2) to check if a file exists.Benjamin Kramer2012-06-021-2/+1
| | | | | | | | | | | Apart from being slightly cheaper, this fixes a real bug that hits 32 bit linux systems. When passing a file larger than 2G to be linked (which isn't that uncommon with large projects such as WebKit), clang's driver checks if the file exists but the file size doesn't fit in an off_t and stat(2) fails with EOVERFLOW. Clang then says that the file doesn't exist instead of passing it to the linker. llvm-svn: 157891
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-0237-49/+49
| | | | llvm-svn: 157885
* PR1255: case ranges.Stepan Dyatkovskiy2012-06-026-17/+16
| | | | | | IntRange converted from struct to class. So main change everywhere is replacement of ".Low/High" with ".getLow/getHigh()" llvm-svn: 157884
* PR1255: case ranges.Stepan Dyatkovskiy2012-06-021-1/+1
| | | | | | IntegersSubsetGeneric, IntegersSubsetMapping: added IntTy template parameter, that allows use either APInt or IntItem. This change allows to write unittest for these classes. llvm-svn: 157880
* Fix a bug in the code which custom-lowers truncating stores in LegalizeDAG.Akira Hatanaka2012-06-021-2/+3
| | | | | | | Check that the SDValue TargetLowering::LowerOperation returns is not null before replacing the original node with the returned node. llvm-svn: 157873
* remove an unused variable.Chris Lattner2012-06-021-1/+1
| | | | llvm-svn: 157872
* Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-023-171/+0
| | | | llvm-svn: 157867
* Set operation actions for load/store nodes in the Mips backend.Akira Hatanaka2012-06-021-0/+11
| | | | llvm-svn: 157866
* Add definitions of 32/64-bit unaligned load/store instructions for Mips.Akira Hatanaka2012-06-022-27/+70
| | | | llvm-svn: 157865
* Define functions MipsTargetLowering::LowerLOAD and LowerSTORE whichAkira Hatanaka2012-06-022-0/+140
| | | | | | custom-lower unaligned load and store nodes. llvm-svn: 157864
* Define Mips specific unaligned load/store nodes.Akira Hatanaka2012-06-023-1/+40
| | | | llvm-svn: 157863
* Expand unaligned i16 loads/stores for the Mips backend.Akira Hatanaka2012-06-021-1/+0
| | | | | | | | This is the first of a series of patches which make changes to the backend to emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction selection. llvm-svn: 157862
* In MipsMCInstLower::LowerSymbolOperand, get offset from symbol ifAkira Hatanaka2012-06-021-2/+4
| | | | | | the MachineOperand type has a valid offset. llvm-svn: 157861
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-0133-214/+188
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
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