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* [InstCombine] simplify fneg+fadd folds; NFCSanjay Patel2018-04-163-26/+7
| | | | | | | | Two cleanups: 1. As noted in D45453, we had tests that don't need FMF that were misplaced in the 'fast-math.ll' test file. 2. This removes the final uses of dyn_castFNegVal, so that can be deleted. We use 'match' now. llvm-svn: 330126
* [InstCombine] fix formatting; NFCSanjay Patel2018-04-161-4/+2
| | | | llvm-svn: 330124
* [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32Dmitry Preobrazhensky2018-04-162-1/+27
| | | | | | | | | See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356 Differential Revision: https://reviews.llvm.org/D45446 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 330123
* [AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.Sander de Smalen2018-04-166-3/+68
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45624 llvm-svn: 330120
* [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.Sander de Smalen2018-04-166-3/+69
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45623 llvm-svn: 330116
* [mips] Restrict certain trap instructions for micromipsr6Stefan Maksimovic2018-04-161-8/+14
| | | | | | | | | Instructions removed from micromipsr6: teqi, tgei, tgeiu, tlti, tltiu, tnei Differential Revision: https://reviews.llvm.org/D45318 llvm-svn: 330114
* [MIR-Canon] Adding ISA-Agnostic COPY Folding.Puyan Lotfi2018-04-161-0/+43
| | | | | | | | | | | | | | | | | Transforms the following: %vreg1234:gpr32 = COPY %42 %vreg1235:gpr32 = COPY %vreg1234 %vreg1236:gpr32 = COPY %vreg1235 $w0 = COPY %vreg1236 into: $w0 = COPY %42 Assuming %42 is also a gpr32 llvm-svn: 330113
* [NFC][MIR-Canon] clang-format cleanup of Mir Canonicalizer Pass.Puyan Lotfi2018-04-161-66/+60
| | | | llvm-svn: 330111
* [X86] Introduce archs: goldmont-plus & tremontGabor Buella2018-04-163-14/+46
| | | | | | | | | | | | | | | Using Goldmont's cost tables for these two upcoming atom archs. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45612 llvm-svn: 330109
* [AArch64][SVE] Asm: Support for structured LD2 (scalar+imm) load instructions.Sander de Smalen2018-04-166-4/+102
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45622 llvm-svn: 330108
* Rename ObjectMemoryBuffer to SmallVectorMemoryBuffer; NFCIWeiming Zhao2018-04-164-7/+7
| | | | | | | | | | | | | | Summary: As discussed in https://reviews.llvm.org/D45606, it makes more sense to name the class as SmallVectorMemoryBuffer Reviewers: bkramer, dblaikie Reviewed By: dblaikie Subscribers: mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45661 llvm-svn: 330107
* [BasicAA] Return MayAlias for the pointer plus variable offset toShiva Chen2018-04-161-6/+6
| | | | | | | | structure object member Differential Revision: https://reviews.llvm.org/D45510 llvm-svn: 330106
* [X86] Use APInt::isSubsetof instead of APInt::intersects to avoid a negation ↵Craig Topper2018-04-151-2/+2
| | | | | | of an APInt value. NFC llvm-svn: 330105
* [X86] Use uint32_t instead of unsigned in GetLo32XForm for readability. NFCCraig Topper2018-04-151-1/+1
| | | | | | GetLo8XForm right next to it uses uint8_t so uint32_t is consistent. llvm-svn: 330104
* [InstCombine] Simplify 'xor' to 'or' if no common bits are set.Roman Lebedev2018-04-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Summary: In order to get the whole fold as specified in [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]], let's first handle the simple straight-forward things. Let's start with the `and` -> `or` simplification. The one obvious thing missing here: the constant mask is not handled. I have an idea how to handle it, but it will require some thinking, and is not strictly required here, so i've left that for later. https://rise4fun.com/Alive/Pkmg Reviewers: spatel, craig.topper, eli.friedman, jingyue Reviewed By: spatel Subscribers: llvm-commits Was reviewed as part of https://reviews.llvm.org/D45631 llvm-svn: 330103
* [SelectionDAG][NFC] haveNoCommonBitsSet(): add FIXME notesRoman Lebedev2018-04-151-0/+2
| | | | | | As suggested in https://reviews.llvm.org/D45631#1068338 llvm-svn: 330102
* [InstCombine] Simplify 'add' to 'or' if no common bits are set.Roman Lebedev2018-04-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: In order to get the whole fold as specified in [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]], let's first handle the simple straight-forward things. Let's start with the `and` -> `or` simplification. The one obvious thing missing here: the constant mask is not handled. I have an idea how to handle it, but it will require some thinking, and is not strictly required here, so i've left that for later. https://rise4fun.com/Alive/Pkmg Reviewers: spatel, craig.topper, eli.friedman, jingyue Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45631 llvm-svn: 330101
* [NFC] ConstantOffsetExtractor::CanTraceInto(): add FIXME: no testsRoman Lebedev2018-04-151-0/+2
| | | | | | | | As suggested in https://reviews.llvm.org/D45631#1068338, looking at haveNoCommonBitsSet() users, and *trying* to show the change effect elsewhere. llvm-svn: 330100
* [MC] Moved all the remaining logic that computed instruction latency and ↵Andrea Di Biagio2018-04-153-52/+48
| | | | | | | | | | reciprocal throughput from TargetSchedModel to MCSchedModel. TargetSchedModel now always delegates to MCSchedModel the computation of instruction latency and reciprocal throughput. No functional change intended. llvm-svn: 330099
* [DAGCombiner, PowerPC] allow X - (fpext(-Y) --> X + fpext(Y) with multiple usesSanjay Patel2018-04-151-6/+6
| | | | | | | | | | | | | This is a transform that I limited in instcombine in rL329821 because it was creating more instructions in IR when the cast has multiple uses. But if the cast is free, then we can do the transform regardless of other uses because it improves the potential throughput of the calculation by removing a dependency on the fneg. Differential Revision: https://reviews.llvm.org/D45598 llvm-svn: 330098
* [InstCombine] simplify more code for distributive property; NFCISanjay Patel2018-04-151-38/+20
| | | | | | | Also, fix capitalization to current style. Follow-up to: rL330096 llvm-svn: 330097
* [InstCombine] simplify code for distributive property; NFCISanjay Patel2018-04-151-19/+3
| | | | llvm-svn: 330096
* [Support] Extend WithColor helpersJonas Devlieghere2018-04-152-15/+15
| | | | | | | Although printing warnings and errors to stderr is by far the most common case, this patch makes it possible to specify any stream. llvm-svn: 330094
* NFC: Move ObjectMemoryBuffer to supportWeiming Zhao2018-04-154-3/+4
| | | | | | | | | | | | | | | | Summary: Since the class is used by both MCJIT and LTO, it makes more sense to move it to Support lib. This is a follow up patch to r329929 and https://reviews.llvm.org/D45244 Reviewers: bkramer, dblaikie Reviewed By: bkramer Subscribers: mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45606 llvm-svn: 330093
* [DebugInfo] Use WithColor to print errors/warningsJonas Devlieghere2018-04-144-23/+28
| | | | | | | Use the convenience methods from WithColor to consistently print errors and warnings in libDebugInfo. llvm-svn: 330092
* [Support] Add convenience functions to WithColor. NFC.Jonas Devlieghere2018-04-141-0/+12
| | | | | | | | | Create convenience functions for printing error, warning and note to stdout. Previously we had similar functions being used in dsymutil, but given that this pattern is so common it makes sense to make it available globally. llvm-svn: 330091
* [InstCombine] Enable Add/Sub simplifications with only 'reassoc' FMFWarren Ristow2018-04-141-3/+4
| | | | | | | | These simplifications were previously enabled only with isFast(), but that is more restrictive than required. Since r317488, FMF has 'reassoc' to control these cases at a finer level. llvm-svn: 330089
* [X86][MMX] Set PAVG/PHADD/PMIN/PMAX/PSIGN instructions to use same scheduler ↵Simon Pilgrim2018-04-141-12/+12
| | | | | | classes as SSE/AVX llvm-svn: 330085
* [NFC] fix trivial typos in document and commentsHiroshi Inoue2018-04-144-4/+4
| | | | | | "not not" -> "not" etc llvm-svn: 330083
* [WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() callHeejin Ahn2018-04-141-3/+4
| | | | | | | | | | | | | | Summary: InsertPos is within the bacic block `Header`, so `findDebugLoc()` should be called on not `MBB` but `Header` instead. Reviewers: yurydelendik Subscribers: jfb, dschuff, aprantl, sbc100, jgravelle-google, sunfish, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D45648 llvm-svn: 330079
* [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.Craig Topper2018-04-131-0/+20
| | | | | | | | The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed. This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended. llvm-svn: 330078
* MachO: trap unreachable instructionsTim Northover2018-04-133-1/+8
| | | | | | | Debugability is more important than saving 4 bytes to let us to fall through to nonense. llvm-svn: 330073
* [DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI duplication bugs of ↵Roman Tereshin2018-04-132-68/+32
| | | | | | CloneModule" llvm-svn: 330070
* [DebugInfo][OPT] Fixing a couple of DI duplication bugs of CloneModuleRoman Tereshin2018-04-133-4/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As demonstrated by the regression tests added in this patch, the following cases are valid cases: 1. A Function with no DISubprogram attached, but various debug info related to its instructions, coming, for instance, from an inlined function, also defined somewhere else in the same module; 2. ... or coming exclusively from the functions inlined and eliminated from the module entirely. The ValueMap shared between CloneFunctionInto calls within CloneModule needs to contain identity mappings for all of the DISubprogram's to prevent them from being duplicated by MapMetadata / RemapInstruction calls, this is achieved via DebugInfoFinder collecting all the DISubprogram's. However, CloneFunctionInto was missing calls into DebugInfoFinder for functions w/o DISubprogram's attached, but still referring DISubprogram's from within (case 1). This patch fixes that. The fix above, however, exposes another issue: if a module contains a DISubprogram referenced only indirectly from other debug info metadata, but not attached to any Function defined within the module (case 2), cloning such a module causes a DICompileUnit duplication: it will be moved in indirecty via a DISubprogram by DebugInfoFinder first (because of the first bug fix described above), without being self-mapped within the shared ValueMap, and then will be copied during named metadata cloning. So this patch makes sure DebugInfoFinder visits DICompileUnit's referenced from DISubprogram's as it goes w/o re-processing llvm.dbg.cu list over and over again for every function cloned, and makes sure that CloneFunctionInto self-maps DICompileUnit's referenced from the entire function, not just its own DISubprogram attached that may also be missing. The most convenient way of tesing CloneModule I found is to rely on CloneModule call from `opt -run-twice`, instead of writing tedious unit tests. That feature has a couple of properties that makes it hard to use for this purpose though: 1. CloneModule doesn't copy source filename, making `opt -run-twice` report it as a difference. 2. `opt -run-twice` does the second run on the original module, not its clone, making the result of cloning completely invisible in opt's actual output with and without `-run-twice` both, which directly contradicts `opt -run-twice`s own error message. This patch fixes this as well. Reviewed By: aprantl Reviewers: loladiro, GorNishanov, espindola, echristo, dexonsmith Subscribers: vsk, debug-info, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D45593 llvm-svn: 330069
* [Hexagon] Initial instruction cost model for auto-vectorizationKrzysztof Parzyszek2018-04-132-98/+195
| | | | llvm-svn: 330065
* Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into ↵Peter Collingbourne2018-04-132-68/+15
| | | | | | | | | | addresses." Caused a hang and eventually an assertion failure in LTO builds of 7zip-benchmark on aarch64 iOS targets. http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/ llvm-svn: 330063
* [LV] Introduce TTI::getMinimumVFKrzysztof Parzyszek2018-04-134-0/+16
| | | | | | | | | | | The function getMinimumVF(ElemWidth) will return the minimum VF for a vector with elements of size ElemWidth bits. This value will only apply to targets for which TTI::shouldMaximizeVectorBandwidth returns true. The value of 0 indicates that there is no minimum VF. Differential Revision: https://reviews.llvm.org/D45271 llvm-svn: 330062
* [DebugInfo] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-131-1/+1
| | | | | | | | | | | | | | | r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. llvm-svn: 330061
* [Power9] Add the TLS store instructions to the Power 9 modelStefan Pintilie2018-04-132-2/+2
| | | | | | | | | | | The Power 9 scheduler model should now include the TLS instructions. We can now, once again, mark the model as complete. From now on, if instructions are added to Power 9 but are not added to the model the build should produce an error. Hopefully that will alert the developer who is adding new instructions that they should also be added to the scheulder model. llvm-svn: 330060
* [Transforms] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-1323-84/+89
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: kcc, pcc, danielcdh, jmolloy, sanjoy, dberlin, ruiu Reviewed By: ruiu Subscribers: ruiu, llvm-commits Differential Revision: https://reviews.llvm.org/D45142 llvm-svn: 330059
* [MC] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-132-6/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: grosbach, void, ruiu Reviewed By: ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45138 llvm-svn: 330058
* [ProfileData] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-133-6/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: bogner, vsk, eraman, ruiu Reviewed By: ruiu Subscribers: ruiu, llvm-commits Differential Revision: https://reviews.llvm.org/D45139 llvm-svn: 330057
* [LTO] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-131-6/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer D44363 for a list of all the required patches. Reviewers: pcc, mehdi_amini, ruiu Reviewed By: ruiu Subscribers: ruiu, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45137 llvm-svn: 330053
* Define InitLLVM to do common initialization all at once.Rui Ueyama2018-04-132-0/+49
| | | | | | | | | | | We have a few functions that virtually all command wants to run on process startup/shutdown. This patch adds InitLLVM class to do that all at once, so that we don't need to copy-n-paste boilerplate code to each llvm command's main() function. Differential Revision: https://reviews.llvm.org/D45602 llvm-svn: 330046
* hwasan: add -fsanitize=kernel-hwaddress flagAndrey Konovalov2018-04-132-15/+29
| | | | | | | | | This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables -hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff. Differential Revision: https://reviews.llvm.org/D45046 llvm-svn: 330044
* [mips] Materialize constants for multiplicationSimon Dardis2018-04-131-3/+76
| | | | | | | | | | | | | | | | | | | | | | | Previously, the MIPS backend would alwyas break down constant multiplications into a series of shifts, adds, and subs. This patch changes that so the cost of doing so is estimated. The cost is estimated against worst case constant materialization and retrieving the results from the HI/LO registers. For cases where the value type of the multiplication is not legal, the cost of legalization is estimated and is accounted for before performing the optimization of breaking down the constant This resolves PR36884. Thanks to npl for reporting the issue! Reviewers: abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D45316 llvm-svn: 330037
* [X86] Remove remaining itinerary support from instructions and target (PR37093)Simon Pilgrim2018-04-133-13/+0
| | | | llvm-svn: 330035
* [ARM] FP16 vmaxnm/vminnm scalar instructionsSjoerd Meijer2018-04-133-2/+20
| | | | | | | | | This adds code generation support for the FP16 vmaxnm/vminnm scalar instructions. Differential Revision: https://reviews.llvm.org/D44675 llvm-svn: 330034
* [ARC] Add LImm support for J/JLYan Luo2018-04-131-5/+17
| | | | llvm-svn: 330031
* [X86] Generalize X86FixupLEAs to work with TargetSchedModelSimon Pilgrim2018-04-131-3/+4
| | | | | | Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call. llvm-svn: 330030
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