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* TargetLoweringBase: Followup to r321035Matthias Braun2017-12-191-2/+3
| | | | | | | | | I missed some prefixes and the fact that on AArch64 we use "bzero" instead of "__bzero" as on X86 when doing my refactoring in r321035. Improve tests for bzero. llvm-svn: 321046
* TargetLowering: Fix InitLibcallCallingConvs() overriding things set in ↵Matthias Braun2017-12-191-7/+3
| | | | | | | | | | | | | InitLibcalls() I missed the fact that the later called InitLibcallCallingConvs() overrides some things set in InitLibcalls() when I did the refactoring in r321036. Fix by merging InitLibcallCallingConvs() into InitLibcalls() and doing the initialization earlier. llvm-svn: 321045
* TargetLoweringBase: Remove unnecessary watchos exception; NFCMatthias Braun2017-12-181-3/+4
| | | | | | | WatchOS isn't report as iOS (as opposed to tvos) so the exception I added in my last commit wasn't necessary after all. llvm-svn: 321041
* [X86] Don't use NOPL when the assembler is passed an empty CPU string.Craig Topper2017-12-181-1/+1
| | | | | | This recommits the change from r321026. I have a fix for the lld test now. llvm-svn: 321038
* LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFCMatthias Braun2017-12-1810-11/+11
| | | | | | Filenames should match the name of the class they contain. llvm-svn: 321037
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-188-72/+57
| | | | | | | | | | | Note: - X86ISelLowering: setLibcallName(SINCOS) was superfluous as InitLibcalls() already does it. - ARMISelLowering: Setting libcallnames for sincos/sincosf seemed superfluous as in the darwin case it wouldn't be used while for all other cases InitLibcalls already does it. llvm-svn: 321036
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-187-47/+12
| | | | llvm-svn: 321035
* [Hexagon] Cache loads to select to avoid traversing mutating DAGKrzysztof Parzyszek2017-12-181-12/+29
| | | | llvm-svn: 321034
* Revert part of r321026 "[X86] Don't use NOPL when the assembler is passed an ↵Craig Topper2017-12-181-1/+1
| | | | | | | | empty CPU string." while I investigate how to fix an lld test failure. Looks like lld also needs to pass a -mcpu in some of its tests llvm-svn: 321033
* Fix buffer overrun in WindowsResourceCOFFWriter::writeSymbolTable()Bob Haarman2017-12-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We were using sprintf(..., "$R06X", <some uint32_t>) to create strings that are expected to be exactly length 8, but this results in longer strings if the uint32_t is greater than 0xffffff. This change modifies the behavior as follows: - Uses the loop counter instead of the data offset. This gives us sequential symbol names, avoiding collisions as much as possible. - Masks the value to 0xffffff to avoid generating names longer than 8 bytes. - Uses formatv instead of sprintf. Fixes PR35581. Reviewers: ruiu, zturner Reviewed By: ruiu Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41270 llvm-svn: 321030
* [MachineOutliner][NFC] Gardening: use std::any_of instead of bool + loopJessica Paquette2017-12-181-10/+3
| | | | | | | River Riddle suggested to use std::any_of instead of the bool + loop thing on r320229. This commit does that. llvm-svn: 321028
* [X86] Don't use NOPL when the assembler is passed an empty CPU string. ↵Craig Topper2017-12-181-1/+1
| | | | | | | | | | Update tests to force a CPU with NOPL Empty string should be equivalent to "generic" which doesn't allow NOPL. Force tests to use specificy 'pentiumpro' to guarantee NOPL. Fixes PR35686 llvm-svn: 321026
* Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner2017-12-185-250/+11
| | | | | | | | | | This reverts changes r320992, r320986, r320973, and r320970. r320970 by itself breaks the test case, and the rest depend on it. Test case will land soon. llvm-svn: 321024
* [Analysis] Generate more precise TBAA tags when one access encloses the otherIvan A. Kosarev2017-12-181-6/+17
| | | | | | | | | | | | | | There are cases when two tags with different base types denote accesses to the same direct or indirect member of a structure type. Currently, merging of such tags results in a tag that represents an access to an object that has the type of that member. This patch changes this so that if one of the accesses encloses the other, then the generic tag is the one of the enclosed access. Differential Revision: https://reviews.llvm.org/D39557 llvm-svn: 321019
* [PGO] Fix handling of cold entry count for instrumented PGOTeresa Johnson2017-12-182-2/+7
| | | | | | | | | | | | | | | | | | | | | Summary: In r277849, getEntryCount was changed to return None when the entry count was 0, specifically for SamplePGO where it means no samples were recorded. However, for instrumentation PGO a 0 entry count should be returned directly, since it does mean that the function was completely cold. Otherwise we end up treating these functions conservatively in isFunctionEntryCold() and isColdBB(). Instead, for SamplePGO use -1 when there are no samples, and change getEntryCount to return None when the value is -1. Reviewers: danielcdh, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41307 llvm-svn: 321018
* Fix more inconsistent line endings. NFC.Dimitry Andric2017-12-184-26/+26
| | | | llvm-svn: 321016
* [X86] Minor formatting fix to getHostCPUFeatures. NFCCraig Topper2017-12-181-2/+1
| | | | llvm-svn: 321015
* [MachineOutliner] Recommit r320229Jessica Paquette2017-12-181-60/+174
| | | | | | | LR was undefined entering outlined functions that contain calls. This made the machine verifier unhappy when expensive checks were enabled. This fixes that. llvm-svn: 321014
* [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
| | | | | | This has the same issue as the early pass disabled in r321010. llvm-svn: 321013
* Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson2017-12-183-14/+41
| | | | | | | | | | | Adds missing support for DW_FORM_data16. Update of r320852/r320886, fixing the unittest again, this time use a raw char string for the test data. Differential Revision: https://reviews.llvm.org/D41090 llvm-svn: 321011
* [PPC] Disable reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
| | | | | | It creates invalid instructions. PR35688. llvm-svn: 321010
* Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC.Dimitry Andric2017-12-181-7/+7
| | | | llvm-svn: 321009
* [Hexagon] Higher versions of HVX imply presence of lower versionsKrzysztof Parzyszek2017-12-181-6/+6
| | | | | | | The code in Hexagon_MC::completeHVXFeatures wasn't setting all HVX- related features correctly. llvm-svn: 321008
* [IR] Support the new TBAA metadata format in IR verifierIvan A. Kosarev2017-12-181-33/+109
| | | | | | Differential Revision: https://reviews.llvm.org/D40438 llvm-svn: 321007
* Fix inconsistent line endings in ARCDisassembler.cpp. NFC.Dimitry Andric2017-12-181-3/+3
| | | | llvm-svn: 321006
* i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004Krzysztof Parzyszek2017-12-181-1/+2
| | | | llvm-svn: 321005
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-184-0/+38
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [Hexagon] Prefer to widen HVX vectors instead of promotingKrzysztof Parzyszek2017-12-182-0/+14
| | | | llvm-svn: 321002
* Removed unused DominanceFrontierMatt Arsenault2017-12-181-3/+0
| | | | llvm-svn: 321001
* [PGO] add MST min edge selection heuristic to ensure non-zero entry countXinliang David Li2017-12-181-7/+67
| | | | | | Differential Revision: http://reviews.llvm.org/D41059 llvm-svn: 320998
* [YAML] Add support for non-printable charactersFrancis Visoiu Mistrih2017-12-187-22/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LLVM IR function names which disable mangling start with '\01' (https://www.llvm.org/docs/LangRef.html#identifiers). When an identifier like "\01@abc@" gets dumped to MIR, it is quoted, but only with single quotes. http://www.yaml.org/spec/1.2/spec.html#id2770814: "The allowed character range explicitly excludes the C0 control block allowed), the surrogate block #xD800-#xDFFF, #xFFFE, and #xFFFF." http://www.yaml.org/spec/1.2/spec.html#id2776092: "All non-printable characters must be escaped. [...] Note that escape sequences are only interpreted in double-quoted scalars." This patch adds support for printing escaped non-printable characters between double quotes if needed. Should also fix PR31743. Differential Revision: https://reviews.llvm.org/D41290 llvm-svn: 320996
* [IR] Add MDBuilder helpers for the new TBAA metadata formatIvan A. Kosarev2017-12-181-1/+31
| | | | | | | | | | | The new helpers are supposed to be used in clang to generate TBAA information in the new format proposed in this thread: http://lists.llvm.org/pipermail/llvm-dev/2017-November/118748.html Differential Revision: https://reviews.llvm.org/D39956 llvm-svn: 320993
* [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specifiedSander de Smalen2017-12-181-1/+4
| | | | | | | | | | | | | | Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, fhahn, olista01, echristo, efriedma Reviewed By: fhahn Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40363 llvm-svn: 320992
* Reland "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-181-15/+22
| | | | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. This version has the correct commit message. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41183 llvm-svn: 320991
* [Memcpy Loop Lowering] Remove the fixed int8 lowering.Sean Fertile2017-12-183-106/+20
| | | | | | | | Switch over to the lowering that uses target supplied operand types. Differential Revision: https://reviews.llvm.org/D41201 llvm-svn: 320989
* [LVI] Support for ashr in LVIMax Kazantsev2017-12-181-0/+1
| | | | | | | | | | Enhance LVI to analyze the ‘ashr’ binary operation. This leverages the infrastructure in ConstantRange for the ashr operation. Patch by Surya Kumari Jangala! Differential Revision: https://reviews.llvm.org/D40886 llvm-svn: 320983
* [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524Diana Picus2017-12-181-9/+5
| | | | | | | | | r319524 has made more G_MERGE_VALUES/G_UNMERGE_VALUES pairs legal than are supported by the rest of the pipeline. Restrict that to only the cases that we can currently handle: packing 32-bit values into 64-bit ones, when we have hardware FP. llvm-svn: 320980
* [ConstantRange] Support for ashr in ConstantRange computationMax Kazantsev2017-12-181-0/+56
| | | | | | | | | | | Extend the ConstantRange implementation to compute the range of possible values resulting from an arithmetic right shift operation. There will be a follow up patch to leverage this constant range infrastructure in LazyValueInfo. Patch by Surya Kumari Jangala! Differential Revision: https://reviews.llvm.org/D40881 llvm-svn: 320976
* Revert "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-181-22/+15
| | | | | | This reverts commit r320974. The commit message lacked the Differential Revison: line. llvm-svn: 320975
* [mips] Fix the target specific instruction verifierSimon Dardis2017-12-181-15/+22
| | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. Reviewers: atanasyan https://reviews.llvm.org/D41183 llvm-svn: 320974
* [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)Sander de Smalen2017-12-182-0/+68
| | | | | | | | | | | | | | Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40361 llvm-svn: 320973
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-12-183-10/+178
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 320970
* [ThinLTO] Remove unused codeEugene Leviant2017-12-181-14/+0
| | | | | | | This is a re-commit of r320464, after patch for gold plugin was landed. llvm-svn: 320968
* AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover2017-12-184-2/+39
| | | | | | | | | | | For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare circumstances. Work around the issue conservatively by avoiding the instruction entirely. This patch changes CodeGen so that problematic instructions are never generated, and the AsmParser so that an equivalent instruction is used (with a warning). llvm-svn: 320965
* [TargetLibraryInfo] Discard library functions with incorrectly sized integersIgor Laevsky2017-12-181-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D41184 llvm-svn: 320964
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-181-0/+144
| | | | | | | | | | | | | Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 llvm-svn: 320962
* [NFC][CodeGen][ExpandMemCmp] Fix documentation.Clement Courbet2017-12-181-3/+2
| | | | llvm-svn: 320960
* [SROA] Disable non-whole-alloca splits by defaultHiroshi Inoue2017-12-181-1/+6
| | | | | | | This patch introduce a switch to control splitting of non-whole-alloca slices with default off. The switch will be default on again after fixing an issue reported in PR35657. llvm-svn: 320958
* [X86] Fix mistake that I made when splitting up the setOperationAction calls ↵Craig Topper2017-12-181-2/+2
| | | | | | | | recently. The block I moved things that need BWI and 512-bit or VLX is incorrectly qualified with just hasBWI || hasVLX. Here I've qualified it with hasBWI && (hasAVX512 || hasVLX) where the hasAVX512 will be replaced with allowing 512-bit vectors in an upcoming patch. llvm-svn: 320957
* [CGP] Fix the handling select inst in complex addressing modeSerguei Katkov2017-12-181-2/+2
| | | | | | | | | | | | | | | When we put the value in select placeholder we must pass the value through simplification tracker due to the value might be already simplified and erased. This is a fix for PR35658. Reviewers: john.brawn, uabelho Reviewed By: john.brawn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41251 llvm-svn: 320956
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