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* [SDAG] commute setcc operands to match a subtractSanjay Patel2019-07-101-0/+11
| | | | | | | | | | | | | | | | | | | If we have: R = sub X, Y P = cmp Y, X ...then flipping the operands in the compare instruction can allow using a subtract that sets compare flags. Motivated by diffs in D58875 - not sure if this changes anything there, but this seems like a good thing independent of that. There's a more involved version of this transform already in IR (in instcombine although that seems misplaced to me) - see "swapMayExposeCSEOpportunities()". Differential Revision: https://reviews.llvm.org/D63958 llvm-svn: 365711
* NFC: Pass DataLayout into isBytewiseValueVitaly Buka2019-07-103-12/+14
| | | | | | | | | | | | | | | | | | Summary: We will need to handle IntToPtr which I will submit in a separate patch as it's not going to be NFC. Reviewers: eugenis, pcc Reviewed By: eugenis Subscribers: hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D63940 llvm-svn: 365709
* [X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.Craig Topper2019-07-101-6/+19
| | | | | | Fixes similar issues to r352306. llvm-svn: 365705
* [X86] Add BLSR and BLSMSK to isUseDefConvertible.Craig Topper2019-07-101-1/+6
| | | | | | | | | | | | Unfortunately subo formation in CGP prevents obvious ways of testing this. But we already have BLSI in here and the flag behavior is well understood. Might become more useful if we improve PR42571. llvm-svn: 365702
* [NFC]Fix IR/MC depency issue for function descriptor SDAG implementationDavid Tenty2019-07-101-44/+35
| | | | | | | | | | | | | | | | | | Summary: llvm/IR/GlobalValue.h can't be included in MC, that creates a circular dependency between MC and IR libraries. This circular dependency is causing an issue for build system that enforce layering. Author: Xiangling_L Reviewers: sfertile, jasonliu, hubert.reinterpretcast, gribozavr Reviewed By: gribozavr Subscribers: wuzish, nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64445 llvm-svn: 365701
* [X86] Remove unused variable. NFCCraig Topper2019-07-101-1/+0
| | | | llvm-svn: 365697
* [AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and ↵Amara Emerson2019-07-102-4/+18
| | | | | | | | | | | | | | | | | | | | unknown values. Since we have distinct types for pointers and scalars, G_INTTOPTRs can sometimes obstruct attempts to find constant source values. These usually come about when try to do some kind of null pointer check. Teaching getConstantVRegValWithLookThrough about this operation allows the CBZ/CBNZ optimization to catch more cases. This change also improves the case where we can't find a constant source at all. Previously we would emit a cmp, cset and tbnz for that. Now we try to just emit a cmp and conditional branch, saving an instruction. The cumulative code size improvement of this change plus D64354 is 5.5% geomean on arm64 CTMark -O0. Differential Revision: https://reviews.llvm.org/D64377 llvm-svn: 365690
* Revert "[ELF] Loose a condition for relocation with a symbol"Nikola Prica2019-07-101-0/+5
| | | | | | | | This reverts commit 8507eca1647118e73435b0ce1de8a1952a021d01. Reveting due to some suspicious failurse in santizer-x86_64-linux. llvm-svn: 365685
* [GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromRegJessica Paquette2019-07-101-14/+3
| | | | | | | | | | | | | | | | Some minor cleanup. This function in Utils does the same thing as `findMIFromReg`. It also looks through copies, which `findMIFromReg` didn't. Delete `findMIFromReg` and use `getOpcodeDef` instead. This only happens in `tryOptVectorDup` right now. Update opt-shuffle-splat to show that we can look through the copies now, too. Differential Revision: https://reviews.llvm.org/D64520 llvm-svn: 365684
* [GlobalISel][AArch64][NFC] Use getDefIgnoringCopies from Utils where we canJessica Paquette2019-07-101-22/+5
| | | | | | | | | | | | | | | | | There are a few places where we walk over copies throughout AArch64InstructionSelector.cpp. In Utils, there's a function that does exactly this which we can use instead. Note that the utility function works with the case where we run into a COPY from a physical register. We've run into bugs with this a couple times, so using it should defend us from similar future bugs. Also update opt-fold-compare.mir to show that we still handle physical registers properly. Differential Revision: https://reviews.llvm.org/D64513 llvm-svn: 365683
* Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"David Greene2019-07-108-38/+37
| | | | | | | | This broke some PPC prefetching tests. This reverts commit 9fdfb045ae8bb643ab0d0455dcf9ecaea3b1eb3c. llvm-svn: 365680
* Move three folds for FADD, FSUB and FMUL in the DAG combiner away from ↵Michael Berg2019-07-101-4/+4
| | | | | | | | | | | | | | | | Unsafe to more aligned checks that reflect context Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang. I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it. Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context. Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm Reviewed By: arsenm Subscribers: michele.scandale, wdng, javed.absar Differential Revision: https://reviews.llvm.org/D64450 llvm-svn: 365679
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-07-108-37/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the TTI cache and software prefetching APIs to prepare for the introduction of a general system model. Changes include: - Marking existing interfaces const and/or override as appropriate - Adding comments - Adding BasicTTIImpl interfaces that delegate to a subtarget implementation - Adding a default "no information" subtarget implementation Only a handful of targets use these interfaces currently: AArch64, Hexagon, PPC and SystemZ. AArch64 already has a custom subtarget implementation, so its custom TTI implementation is migrated to use the new facilities in BasicTTIImpl to invoke its custom subtarget implementation. The custom TTI implementations continue to exist for the other targets with this change. They are not moved over to subtarget-based implementations. The end goal is to have the default subtarget implementation defer to the system model defined by the target. With this change, the default subtarget implementation essentially returns "no information" for these interfaces. None of the existing users of TTI will hit that implementation because they define their own custom TTI implementations and won't use the BasicTTIImpl implementations. Once system models are in place for the targets that use these interfaces, their custom TTI implementations can be removed. Differential Revision: https://reviews.llvm.org/D63614 llvm-svn: 365676
* Recommit "[CommandLine] Remove OptionCategory and SubCommand caches from the ↵Don Hinton2019-07-101-59/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | Option class." Previously reverted in 364141 due to buildbot breakage, and fixed here by making GeneralCategory global a ManagedStatic. Summary: This change processes `OptionCategory`s and `SubCommand`s as they are seen instead of caching them in the Option class and processing them later. Doing so simplifies the work needed to be done by the Global parser and significantly reduces the size of the Option class to a mere 64 bytes. Removing the `OptionCategory` cache saved 24 bytes, and removing the `SubCommand` cache saved an additional 48 bytes, for a total of a 72 byte reduction. Reviewed By: serge-sans-paille Tags: #llvm, #clang Differential Revision: https://reviews.llvm.org/D62105 llvm-svn: 365675
* [X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.Simon Pilgrim2019-07-101-14/+12
| | | | | | Determine the element/load size calculations earlier and assert that they are whole bytes in size. llvm-svn: 365674
* [LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.Alina Sbirlea2019-07-101-4/+8
| | | | | | | | | | | | | | | | | | | | Summary: The map kept in loop rotate is used for instruction remapping, in order to simplify the clones of instructions. Thus, if an instruction can be simplified, its simplified value is placed in the map, even when the clone is added to the IR. MemorySSA in contrast needs to know about that clone, so it can add an access for it. To resolve this: keep a different map for MemorySSA. Reviewers: george.burgess.iv Subscribers: jlebar, Prazek, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63680 llvm-svn: 365672
* [ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.Lang Hames2019-07-101-44/+35
| | | | | | | | | | LLJITBuilder now has a setCompileFunctionCreator method which can be used to construct a CompileFunction for the LLJIT instance being created. The motivating use-case for this is supporting ObjectCaches, which can now be set up at compile-function construction time. To demonstrate this an example project, LLJITWithObjectCache, is included. llvm-svn: 365671
* [TargetLowering] support BlockAddress as "i" inline asm constraintNick Desaulniers2019-07-101-0/+7
| | | | | | | | | | | | | | | | | | | | Summary: This allows passing address of labels to inline assembly "i" input constraints. Fixes pr/42502. Reviewers: ostannard Reviewed By: ostannard Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D64167 llvm-svn: 365664
* MC: AArch64: Add support for pg_hi21_nc relocation specifier.Peter Collingbourne2019-07-101-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D64455 llvm-svn: 365661
* [CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)Vedant Kumar2019-07-101-13/+29
| | | | | | | | | | | | | | An alloca which can be sunk into the extraction region may have more than one bitcast use. Move these uses along with the alloca to prevent use-before-def. Testing: check-llvm, stage2 build of clang Fixes llvm.org/PR42451. Differential Revision: https://reviews.llvm.org/D64463 llvm-svn: 365660
* [CodeExtractor] Simplify findAllocas, NFCVedant Kumar2019-07-101-73/+91
| | | | | | | | | Split getLifetimeMarkers out into its own method and have it return a struct. Differential Revision: https://reviews.llvm.org/D64467 llvm-svn: 365659
* GlobalISel: Legalization for G_FMINNUM/G_FMAXNUMMatt Arsenault2019-07-104-1/+128
| | | | llvm-svn: 365658
* GlobalISel: Define the full family of FP min/max instructionsMatt Arsenault2019-07-101-0/+8
| | | | llvm-svn: 365657
* [X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.Simon Pilgrim2019-07-101-6/+0
| | | | | | We've already checked that each element is the correct contributory size for VT when we inspect the elements for Undef/Zero/Load. llvm-svn: 365656
* [X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same ↵Simon Pilgrim2019-07-101-3/+5
| | | | | | | | size. NFCI. This renames the type so it doesn't sound like its based off the load size - as we're moving towards supporting combining loads of different sizes. llvm-svn: 365655
* AMDGPU: Serialize mode from MachineFunctionInfoMatt Arsenault2019-07-103-1/+32
| | | | llvm-svn: 365653
* [PatternMatch] Generalize m_SpecificInt_ULT() to take ICmpInst::PredicateRoman Lebedev2019-07-102-2/+4
| | | | | | | As discussed in the original review, this may be useful, so let's just do it. llvm-svn: 365652
* [Remarks] Add cl::Hidden to -remarks-yaml-string-tableFrancis Visoiu Mistrih2019-07-101-2/+3
| | | | | | It was showing up in a lot of unrelated tools. llvm-svn: 365647
* [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32Jay Foad2019-07-101-7/+8
| | | | | | | | | | | | | | | | | Summary: D59191 added support for these modifiers in the assembler and disassembler. This patch just teaches instruction selection that it can use them. Reviewers: arsenm, tstellar Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64497 llvm-svn: 365640
* [InstCombine] pow(C,x) -> exp2(log2(C)*x)David Bolvansky2019-07-101-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Transform pow(C,x) To exp2(log2(C)*x) if C > 0, C != inf, C != NaN (and C is not power of 2, since we have some fold for such case already). log(C) is folded by the compiler and exp2 is much faster to compute than pow. Reviewers: spatel, efriedma, evandro Reviewed By: evandro Subscribers: lebedev.ri, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64099 llvm-svn: 365637
* [X86] EltsFromConsecutiveLoads - cleanup Zero/Undef/Load element collection. ↵Simon Pilgrim2019-07-101-12/+17
| | | | | | NFCI. llvm-svn: 365628
* [MIPS GlobalISel] Select float and double phiPetar Avramovic2019-07-101-4/+25
| | | | | | | | Select float and double phi for MIPS32. Differential Revision: https://reviews.llvm.org/D64420 llvm-svn: 365627
* [MIPS GlobalISel] Select float and double load and storePetar Avramovic2019-07-101-22/+44
| | | | | | | | Select float and double load and store for MIPS32. Differential Revision: https://reviews.llvm.org/D64419 llvm-svn: 365626
* [FileCheck] Simplify numeric variable interfaceThomas Preud'homme2019-07-101-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch simplifies 2 aspects in the FileCheckNumericVariable code. First, setValue() method is turned into a void function since being called only on undefined variable is an invariant and is now asserted rather than returned. This remove the assert from the callers. Second, clearValue() method is also turned into a void function since the only caller does not check its return value since it may be trying to clear the value of variable that is already cleared without this being noteworthy. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya Tags: #llvm Differential Revision: https://reviews.llvm.org/D64231 > llvm-svn: 365249 llvm-svn: 365625
* [FileCheck] Fix @LINE value after match failureThomas Preud'homme2019-07-101-1/+3
| | | | | | | | | | | | | | | | | | | | Summary: The value of the FileCheckNumericVariable class instance representing the @LINE numeric variable is set and cleared respectively before and after substitutions are made, if any. However, when a substitution fails, the value is not cleared. This causes the next substitution of @LINE later on to give the wrong value since setValue is a nop if the value is already set. This is what caused failures after commit r365249. Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield Tags: #llvm Differential Revision: https://reviews.llvm.org/D64449 llvm-svn: 365624
* [NFC][ARM] Convert lambdas to static helpersSam Parker2019-07-101-57/+73
| | | | | | | Break up and convert some of the lambdas in ARMLowOverheadLoops into static functions. llvm-svn: 365623
* [X86] EltsFromConsecutiveLoads - LDBase is non-null. NFCI.Simon Pilgrim2019-07-101-6/+4
| | | | | | Don't bother checking for LDBase != null - it should be (and we assert that it is). llvm-svn: 365622
* [DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.Simon Pilgrim2019-07-101-1/+1
| | | | | | Keep the uint64_t type from getZExtValue() to stop truncation/extension overflow warnings in MSVC in subvector index math. llvm-svn: 365621
* [X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.Simon Pilgrim2019-07-101-9/+9
| | | | | | Cache the LoadSDNode nodes so we can easily map to/from the element index instead of packing them together - this will be useful for future patches for PR16739 etc. llvm-svn: 365620
* [ELF] Loose a condition for relocation with a symbolNikola Prica2019-07-101-5/+0
| | | | | | | | | | | | | | | | | Deleted code was introduced as a work around for a bug in the gold linker (http://sourceware.org/PR16794). Test case that was given as a reason for this part of code, the one on previous link, now works for the gold. This condition is too strict and when a code is compiled with debug info it forces generation of numerous relocations with symbol for architectures that do not have relocation addend. Reviewers: arsenm, espindola Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D64327 llvm-svn: 365618
* [X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable supportSimon Pilgrim2019-07-101-7/+15
| | | | | | | | | | This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it. Another step towards partial vector loads...... Differential Revision: https://reviews.llvm.org/D64205 llvm-svn: 365614
* Fix const/non-const lambda return type warning. NFCI.Simon Pilgrim2019-07-101-1/+1
| | | | llvm-svn: 365613
* Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.Simon Pilgrim2019-07-101-1/+1
| | | | llvm-svn: 365612
* [SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with ↵Serguei Katkov2019-07-101-1/+1
| | | | | | | | | | | | | | | one unique successor Only instructions with two or more unique successors should be considered for unswitching. Patch Author: Daniil Suchkov. Reviewers: reames, asbirlea, skatkov Reviewed By: skatkov Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D64404 llvm-svn: 365611
* [ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is presentMikhail Maltsev2019-07-102-5/+5
| | | | | | | | | | | | | | | | | | | | Summary: Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to these. Patch by Momchil Velikov. Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen Reviewed By: dmgreen Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64413 llvm-svn: 365604
* [X86] Limit getTargetConstantFromNode to only work on NormalLoads not ↵Craig Topper2019-07-101-1/+1
| | | | | | | | | extending loads. This seems to fix a failure reported by Jordan Rupprecht, but we don't have a reduced test case yet. llvm-svn: 365589
* [Support] Move llvm::MemoryBuffer to sys::fs::file_tReid Kleckner2019-07-1012-96/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: On Windows, Posix integer file descriptors are a compatibility layer over native file handles provided by the C runtime. There is a hard limit on the maximum number of file descriptors that a process can open, and the limit is 8192. LLD typically doesn't run into this limit because it opens input files, maps them into memory, and then immediately closes the file descriptor. This prevents it from running out of FDs. For various reasons, I'd like to open handles to every input file and keep them open during linking. That requires migrating MemoryBuffer over to taking open native file handles instead of integer FDs. Reviewers: aganea, Bigcheese Reviewed By: aganea Subscribers: smeenai, silvas, mehdi_amini, hiraditya, steven_wu, dexonsmith, dang, llvm-commits, zturner Tags: #llvm Differential Revision: https://reviews.llvm.org/D63453 llvm-svn: 365588
* AMDGPU/GlobalISel: Add support for wide loads >= 256-bitsTom Stellard2019-07-104-37/+219
| | | | | | | | | | | | | | | | | | Summary: This adds support for the most commonly used wide load types: <8xi32>, <16xi32>, <4xi64>, and <8xi64> Reviewers: arsenm Reviewed By: arsenm Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57399 llvm-svn: 365586
* GlobalISel: Implement lower for G_FCOPYSIGNMatt Arsenault2019-07-092-3/+52
| | | | | | | | | In SelectionDAG AMDGPU treated these as legal, but this was mostly because the bitcasts required for FP types were painful. Theoretically the bitpattern should eventually match to bfi, so don't bother trying to get the patterns to import. llvm-svn: 365583
* [Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.hFrancis Visoiu Mistrih2019-07-091-0/+2
| | | | | | This fixes a modules issue. llvm-svn: 365580
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