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* Test commit. NFC.Bryant Wong2019-07-121-0/+1
| | | | | | Formatting fix. llvm-svn: 365878
* [mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6Simon Atanasyan2019-07-122-1/+14
| | | | | | | | | | | | | | | | There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 llvm-svn: 365870
* [YAMLIO] Remove trailing spaces when outputting mapsFangrui Song2019-07-121-11/+23
| | | | | | | | | | | | | | | | | | llvm::yaml::Output::paddedKey unconditionally outputs spaces, which are superfluous if the value to be dumped is a sequence or map. Change `bool NeedsNewLine` to `StringRef Padding` so that it can be overridden to `\n` if the value is a sequence or map. An empty map/sequence is special. It is printed as `{}` or `[]` without a newline, while a non-empty map/sequence follows a newline. To handle this distinction, add another variable `PaddingBeforeContainer` and does the special handling in endMapping/endSequence. Reviewed By: grimar, jhenderson Differential Revision: https://reviews.llvm.org/D64566 llvm-svn: 365869
* Return Undef from isBytewiseValue for empty arrays or structsVitaly Buka2019-07-121-0/+4
| | | | | | | | | | | | Reviewers: pcc, eugenis Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64052 llvm-svn: 365864
* [MachinePipeliner] Fix order for nodes with Anti dependence in same cycleJinsong Ji2019-07-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Problem exposed in PowerPC functional testing. We did not consider Anti dependence for nodes in same cycle, so we may end up generating bad machine code. eg: the reduced test won't verify. *** Bad machine code: Using an undefined physical register *** - function: lame_encode_buffer_interleaved - basic block: %bb.4 (0x4bde4e12928) - instruction: %29:gprc = ADDZE %27:gprc, implicit-def dead $carry, implicit $carry - operand 3: implicit $carry Reviewers: bcahoon, kparzysz, hfinkel Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64192 llvm-svn: 365859
* Handle IntToPtr in isBytewiseValueVitaly Buka2019-07-121-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This helps with more efficient use of memset for pattern initialization From @pcc prototype for -ftrivial-auto-var-init=pattern optimizations Binary size change on CTMark, (with -fuse-ld=lld -Wl,--icf=all, similar results with default linker options) ``` master patch diff Os 8.238864e+05 8.238864e+05 0.0 O3 1.054797e+06 1.054797e+06 0.0 Os zero 8.292384e+05 8.292384e+05 0.0 O3 zero 1.062626e+06 1.062626e+06 0.0 Os pattern 8.579712e+05 8.338048e+05 -0.030299 O3 pattern 1.090502e+06 1.067574e+06 -0.020481 ``` Zero vs Pattern on master ``` zero pattern diff Os 8.292384e+05 8.579712e+05 0.036578 O3 1.062626e+06 1.090502e+06 0.025124 ``` Zero vs Pattern with the patch ``` zero pattern diff Os 8.292384e+05 8.338048e+05 0.003333 O3 1.062626e+06 1.067574e+06 0.003193 ``` Reviewers: pcc, eugenis Subscribers: hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D63967 llvm-svn: 365858
* [InstCombine] Reorder pow() transformations (NFC)Evandro Menezes2019-07-121-23/+19
| | | | | | | Move the transformation from `powf(x, itofp(y))` to `powi(x, y)` to the group of transformations related to the exponent. llvm-svn: 365851
* [AMDGPU] Skip calculating callee saved registers for entry function.Michael Liao2019-07-111-1/+5
| | | | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64596 llvm-svn: 365846
* AMDGPU: s_waitcnt field should be treated as unsignedMatt Arsenault2019-07-112-3/+7
| | | | | | | Also make it an ImmLeaf, so it should work with global isel as well, which was part of the point of moving it in the first place. llvm-svn: 365842
* [NewPM] Port SancovLeonard Chan2019-07-114-111/+262
| | | | | | | | | | | | | | | | | This patch contains a port of SanitizerCoverage to the new pass manager. This one's a bit hefty. Changes: - Split SanitizerCoverageModule into 2 SanitizerCoverage for passing over functions and ModuleSanitizerCoverage for passing over modules. - ModuleSanitizerCoverage exists for adding 2 module level calls to initialization functions but only if there's a function that was instrumented by sancov. - Added legacy and new PM wrapper classes that own instances of the 2 new classes. - Update llvm tests and add clang tests. Differential Revision: https://reviews.llvm.org/D62888 llvm-svn: 365838
* [AMDGPU] Fixed asan error with agpr spillingStanislav Mekhanoshin2019-07-111-1/+4
| | | | | | Instruction was used after it was erased. llvm-svn: 365837
* Fix build errors LLVM tests are disabled.Diego Novillo2019-07-111-1/+3
| | | | | | | | | | | | | | | | | | Original patch from alanbaker@google.com Fixes the error: CMake Error in <...>/llvm/cmake/modules/CMakeLists.txt: export called with target "LLVMTestingSupport" which requires target "gtest" that is not in the export set. This occurs when LLVM is embedded in a larger project, but is configured not to include tests. If testing is disabled gtest isn't available and LLVM fails to configure. Differential revision: https://reviews.llvm.org/D63097 llvm-svn: 365836
* [AMDGPU] gfx908 agpr spillingStanislav Mekhanoshin2019-07-117-45/+367
| | | | | | Differential Revision: https://reviews.llvm.org/D64594 llvm-svn: 365833
* [Attributor] Deduce "nosync" function attribute.Stefan Stipanovic2019-07-119-1/+209
| | | | | | | | | | | | | | Introduce and deduce "nosync" function attribute to indicate that a function does not synchronize with another thread in a way that other thread might free memory. Reviewers: jdoerfert, jfb, nhaehnle, arsenm Subscribers: wdng, hfinkel, nhaenhle, mehdi_amini, steven_wu, dexonsmith, arsenm, uenoku, hiraditya, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D62766 llvm-svn: 365830
* [AMDGPU] gfx908 hazard recognizerStanislav Mekhanoshin2019-07-112-1/+233
| | | | | | Differential Revision: https://reviews.llvm.org/D64593 llvm-svn: 365829
* [AMDGPU] gfx908 schedulingStanislav Mekhanoshin2019-07-113-0/+163
| | | | | | Differential Revision: https://reviews.llvm.org/D64590 llvm-svn: 365826
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-1116-62/+548
| | | | | | Differential Revision: https://reviews.llvm.org/D64584 llvm-svn: 365824
* Open native file handles to avoid converting from FDs, NFCReid Kleckner2019-07-115-36/+37
| | | | | | Follow up to r365588. llvm-svn: 365820
* [WebAssembly] Assembler: support negative float constants.Wouter van Oortmerssen2019-07-111-12/+27
| | | | | | | | | | | | Reviewers: dschuff Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64367 llvm-svn: 365802
* [NVPTX] Use atomicrmw fadd instead of intrinsicsBenjamin Kramer2019-07-114-21/+20
| | | | | | AutoUpgrade the old intrinsics to atomicrmw fadd. llvm-svn: 365796
* [X86] Merge negated ISD::SUB nodes into X86ISD::SUB equivalent (PR40483)Sanjay Patel2019-07-111-7/+7
| | | | | | | | | | | Follow up to D58597, where it was noted that the commuted ISD::SUB variant was having problems with lack of combines. See also D63958 where we untangled setcc/sub pairs. Differential Revision: https://reviews.llvm.org/D58875 llvm-svn: 365791
* Fix a few 'no newline at end of file' warnings that Xcode emitsNico Weber2019-07-111-1/+1
| | | | | | | (Xcode even has a snazzy "Fix" button, but clicking that inserts two newlines. So close!) llvm-svn: 365789
* [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS supportSimon Pilgrim2019-07-111-4/+14
| | | | | | | | | | | | | | We already split extract_subvector(binop(insert_subvector(v,x),insert_subvector(w,y))) -> binop(x,y). This patch adds support for extract_subvector(binop(concat_vectors(),concat_vectors())) cases as well. In particular this means we don't have to wait for X86 lowering to convert concat_vectors to insert_subvector chains, which helps avoid some cases where demandedelts/combine calls occur too late to split large vector ops. The fast-isel-store.ll load folding regression is annoying but I don't think is that critical. Differential Revision: https://reviews.llvm.org/D63653 llvm-svn: 365785
* RegUsageInfoCollector: Skip calling conventions I missed beforeMatt Arsenault2019-07-111-0/+3
| | | | llvm-svn: 365784
* AMDGPU/GlobalISel: Move kernel argument handling to separate functionMatt Arsenault2019-07-112-42/+61
| | | | llvm-svn: 365782
* GlobalISel: Use RegisterMatt Arsenault2019-07-111-5/+5
| | | | llvm-svn: 365780
* [InstCombine] don't move FP negation out of a constant expressionSanjay Patel2019-07-111-2/+4
| | | | | | | -(X * ConstExpr) becomes X * (-ConstExpr), so don't reverse that and infinite loop. llvm-svn: 365774
* OpaquePtr: switch to GlobalValue::getValueType in a few places. NFC.Tim Northover2019-07-113-8/+5
| | | | llvm-svn: 365770
* OpaquePtr: use byval accessor instead of inspecting pointer type. NFC.Tim Northover2019-07-111-3/+2
| | | | | | | The accessor can deal with both "byval(ty)" and "ty* byval" forms seamlessly. llvm-svn: 365769
* OpaquePtr: use load instruction directly for type. NFC.Tim Northover2019-07-111-2/+1
| | | | llvm-svn: 365768
* InstructionSimplify: Simplify InstructionSimplify. NFC.Tim Northover2019-07-111-42/+24
| | | | | | | | | | | The interface predates CallBase, so both it and implementation were significantly more complicated than they needed to be. There was even some redundancy that could be eliminated. Should also help with OpaquePointers by not trying to derive a function's type from it's PointerType. llvm-svn: 365767
* [yaml2obj] - Allow overriding the sh_size field.George Rimar2019-07-111-4/+6
| | | | | | | | | | There is no way to set broken sh_size field currently for sections. It can be usefull for writing the test cases. Differential revision: https://reviews.llvm.org/D64401 llvm-svn: 365766
* [InstCombine] Reorder recently added/improved pow transformationsDavid Bolvansky2019-07-111-3/+3
| | | | | | Changed cases are now faster with exp2. llvm-svn: 365758
* Revert [BitcodeReader] Validate OpNum, before accessing Record array.Florian Hahn2019-07-111-4/+0
| | | | | | | | | | | | This reverts r365750 (git commit 8b222ecf2769ee133691f208f6166ce118c4a164) llvm-dis runs out of memory while opening invalid-fcmp-opnum.bc on llvm-hexagon-elf, probably because the bitcode file contains other suspicious values. http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/21949 llvm-svn: 365757
* [llvm-objcopy] Don't change permissions of non-regular output filesFangrui Song2019-07-112-7/+13
| | | | | | | | | | | | | | | | | | | | | | There is currently an EPERM error when a regular user executes `llvm-objcopy a.o /dev/null`. Worse, root can even change the mode bits of /dev/null. Fix it by checking if the output file is special. A new overload of llvm::sys::fs::setPermissions with FD as the parameter is added. Users should provide `perm & ~umask` as the parameter if they intend to respect umask. The existing overload of llvm::sys::fs::setPermissions may be deleted if we can find an implementation of fchmod() on Windows. fchmod() is usually better than chmod() because it saves syscalls and can avoid race condition. Reviewed By: jakehehrlich, jhenderson Differential Revision: https://reviews.llvm.org/D64236 llvm-svn: 365753
* [X86] -fno-plt: use GOT __tls_get_addr only if GOTPCRELX is enabledFangrui Song2019-07-111-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: As of binutils 2.32, ld has a bogus TLS relaxation error when the GD/LD code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is attempted to be relaxed to IE/LE (binutils PR24784). gold and lld are good. In gcc/config/i386/i386.md, there is a configure-time check of as/ld support and the GOT relaxation will not be used if as/ld doesn't support it: if (flag_plt || !HAVE_AS_IX86_TLS_GET_ADDR_GOT) return "call\t%P2"; return "call\t{*%p2@GOT(%1)|[DWORD PTR %p2@GOT[%1]]}"; In clang, -DENABLE_X86_RELAX_RELOCATIONS=OFF is the default. The ld.bfd bogus error can be reproduced with: thread_local int a; int main() { return a; } clang -fno-plt -fpic a.cc -fuse-ld=bfd GOTPCRELX gained relative good support in 2016, which is considered relatively new. It is even difficult to conditionally default to -DENABLE_X86_RELAX_RELOCATIONS=ON due to cross compilation reasons. So work around the ld.bfd bug by only using GOT when GOTPCRELX is enabled. Reviewers: dalias, hjl.tools, nikic, rnk Reviewed By: nikic Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64304 llvm-svn: 365752
* [BitcodeReader] Validate OpNum, before accessing Record array.Florian Hahn2019-07-111-0/+4
| | | | | | | | | | | | | | | Currently invalid bitcode files can cause a crash, when OpNum exceeds the number of elements in Record, like in the attached bitcode file. The test case was generated by clusterfuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15698 Reviewers: t.p.northover, thegameg, jfb Reviewed By: jfb Differential Revision: https://reviews.llvm.org/D64507 llvm-svn: 365750
* [ARM][LowOverheadLoops] Correct offset checkingSam Parker2019-07-113-11/+29
| | | | | | | | | | | | | | | | This patch addresses a couple of problems: 1) The maximum supported offset of LE is -4094. 2) The offset of WLS also needs to be checked, this uses a maximum positive offset of 4094. The use of BasicBlockUtils has been changed because the block offsets weren't being initialised, but the isBBInRange checks both positive and negative offsets. ARMISelLowering has been tweaked because the test case presented another pattern that we weren't supporting. llvm-svn: 365749
* [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.Simon Tatham2019-07-111-3/+0
| | | | | | | | | | | | | | | | | | | | The VQDMLAH.U8, VQDMLAH.U16 and VQDMLAH.U32 instructions don't actually exist: the Armv8.1-M architecture spec only lists signed forms of that instruction. The unsigned ones were added in error: they existed in an early draft of the spec, but they were removed before the public version, and we missed that particular spec change. Also affects the variant forms VQDMLASH, VQRDMLAH and VQRDMLASH. Reviewers: miyuki Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64502 llvm-svn: 365747
* [MIPS GlobalISel] Skip copies in addUseDef and addDefUsesPetar Avramovic2019-07-112-11/+48
| | | | | | | | | | | | Skip copies between virtual registers during search for UseDefs and DefUses. Since each operand has one def search for UseDefs is straightforward. But since operand can have many uses, we have to check all uses of each copy we traverse during search for DefUses. Differential Revision: https://reviews.llvm.org/D64486 llvm-svn: 365744
* [MIPS GlobalISel] RegBankSelect for chains of ambiguous instructionsPetar Avramovic2019-07-112-14/+77
| | | | | | | | | | | | | | | | | | | | When one of the uses/defs of ambiguous instruction is also ambiguous visit it recursively and search its uses/defs for instruction with only one mapping available. When all instruction in a chain are ambiguous arbitrary mapping can be selected. For s64 operands in ambiguous chain fprb is selected since it results in less instructions then having to narrow scalar s64 to s32. For s32 both gprb and fprb result in same number of instructions and gprb is selected like a general purpose option. At the moment we always avoid cross register bank copies. TODO: Implement a model for costs calculations of different mappings on same instruction and cross bank copies. Allow cross bank copies when appropriate according to cost model. Differential Revision: https://reviews.llvm.org/D64485 llvm-svn: 365743
* Revert Recommit "[CommandLine] Remove OptionCategory and SubCommand caches ↵Haojian Wu2019-07-111-53/+59
| | | | | | | | | | from the Option class." This reverts r365675 (git commit 43d75f977853c3ec891a440c362b2df183a211b5) The patch causes a crash in SupportTests (CommandLineTest.AliasesWithArguments). llvm-svn: 365742
* Remove some redundant code from r290372 and improve a comment.Jay Foad2019-07-111-5/+3
| | | | llvm-svn: 365741
* [ARM][ParallelDSP] Change the search for smladsSam Parker2019-07-111-252/+316
| | | | | | | | | | | | | | | | Two functional changes have been made here: - Now search up from any add instruction to find the chains of operations that we may turn into a smlad. This allows the generation of a smlad which doesn't accumulate into a phi. - The search function has been corrected to stop it falsely searching up through an invalid path. The bulk of the changes have been making the Reduction struct a class and making it more C++y with getters and setters. Differential Revision: https://reviews.llvm.org/D61780 llvm-svn: 365740
* [WebAssembly] Print error message for llvm.clear_cache intrinsicHeejin Ahn2019-07-111-0/+4
| | | | | | | | | | | | | | | | Summary: Wasm does not currently support `llvm.clear_cache` intrinsic, and this prints a proper error message instead of segfault. Reviewers: dschuff, sbc100, sunfish Subscribers: jgravelle-google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64322 llvm-svn: 365731
* [SCEV] teach SCEV symbolical execution about overflow intrinsics folding.Chen Zheng2019-07-112-1/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D64422 llvm-svn: 365726
* Replace three "strip & accumulate" implementations with a single oneJohannes Doerfert2019-07-113-97/+32
| | | | | | | | | | | This patch replaces the three almost identical "strip & accumulate" implementations for constant pointer offsets with a single one, combining the respective functionalities. The old interfaces are kept for now. Differential Revision: https://reviews.llvm.org/D64468 llvm-svn: 365723
* [X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.Craig Topper2019-07-111-12/+15
| | | | | | | | | | | | | | | | | We use the functions that convert to three address to do the conversion, but changing an 8 or 16 bit will cause it to create a virtual register. This can't be done after register allocation where this pass runs. I've switched the pass completely to a white list of instructions that can be converted to LEA instead of a blacklist that was incorrect. This will avoid surprises if we enhance the three address conversion function to include additional instructions in the future. Fixes PR42565. llvm-svn: 365720
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-117-4/+195
| | | | | | Differential Revision: https://reviews.llvm.org/D64435 llvm-svn: 365717
* [AMDGPU] gfx908 dot instruction supportStanislav Mekhanoshin2019-07-111-0/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D64431 llvm-svn: 365715
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