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* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-1329-991/+962
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* [DebugInfo] Debug locations for constant SD nodesSergey Dmitrouk2015-05-131-41/+76
| | | | | | | | | | | | | | | | | | | | | Several updates for [DebugInfo] Add debug locations to constant SD nodes (r235989). Includes: * re-enabling the change (disabled recently); * missing change for FP constants; * resetting debug location of constant node if it's used more than at one place to prevent emission of wrong locations in case of coalesced constants; * a couple of additional tests. Now all look ups in CSEMap are wrapped by additional method. Comment in D9084 suggests that debug locations aren't useful for "target constants", so there might be one more change related to this API (namely, dropping debug locations for getTarget*Constant methods). Differential Revision: http://reviews.llvm.org/D9604 llvm-svn: 237237
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-1329-962/+991
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* AVX-512: fixed a bug in encoding of VPSRAQ instrcution,Elena Demikhovsky2015-05-131-1/+1
| | | | | | added a bunch of encoding tests. llvm-svn: 237232
* Use ArrayRef::slice instead of manually constructing an ArrayRef from ↵Craig Topper2015-05-131-6/+1
| | | | | | ArrayRef iterators. NFC llvm-svn: 237231
* Constify arguments to methods in LICM. NFCPete Cooper2015-05-131-25/+33
| | | | llvm-svn: 237227
* Change LoadAndStorePromoter to take ArrayRef instead of SmallVectorImpl&.Pete Cooper2015-05-134-8/+11
| | | | | | | | | | The array passed to LoadAndStorePromoter's constructor was a constant reference to a SmallVectorImpl, which is just the same as passing an ArrayRef. Also, the data in the array can be 'const Instruction*' instead of 'Instruction*'. Its not possible to convert a SmallVectorImpl<T*> to SmallVectorImpl<const T*>, but ArrayRef does provide such a method. Currently this added calls to makeArrayRef which should be a nop, but i'm going to kick off a discussion about improving ArrayRef to not need these. llvm-svn: 237226
* Constify arguments in AliasSetTracker methods. NFCPete Cooper2015-05-131-4/+5
| | | | llvm-svn: 237225
* Change a loop in LoopInfo to foreach. NFCPete Cooper2015-05-131-2/+2
| | | | llvm-svn: 237224
* Constify arguments to methods in LoopInfo. NFCPete Cooper2015-05-131-3/+3
| | | | llvm-svn: 237223
* [PlaceSafepoints] Reduce dominator tree recalculationPhilip Reames2015-05-131-42/+24
| | | | | | | | | | Reduce recalculation of the dominator tree by identifying all sites that will need a safepoint poll before doing any of the insertion. This allows us to invalidate the dominator info once, rather than once per safepoint poll inserted. While I'm at it, update findLocationForEntrySafepoint to properly update the dom tree now that the interface has been made easy. When first written, it wasn't per comment in the code. Differential Revision: http://reviews.llvm.org/D9727 llvm-svn: 237220
* [SLSR] handles non-canonicalized Mul candidatesJingyue Wu2015-05-131-2/+2
| | | | | | | | such as (2 + B) * S. Tested by @non_canonicalized in slsr-mul.ll llvm-svn: 237216
* [Statepoints] Support for "patchable" statepoints.Sanjoy Das2015-05-126-88/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change adds two new parameters to the statepoint intrinsic, `i64 id` and `i32 num_patch_bytes`. `id` gets propagated to the ID field in the generated StackMap section. If the `num_patch_bytes` is non-zero then the statepoint is lowered to `num_patch_bytes` bytes of nops instead of a call (the spill and reload code remains unchanged). A non-zero `num_patch_bytes` is useful in situations where a language runtime requires complete control over how a call is lowered. This change brings statepoints one step closer to patchpoints. With some additional work (that is not part of this patch) it should be possible to get rid of `TargetOpcode::STATEPOINT` altogether. PlaceSafepoints generates `statepoint` wrappers with `id` set to `0xABCDEF00` (the old default value for the ID reported in the stackmap) and `num_patch_bytes` set to `0`. This can be made more sophisticated later. Reviewers: reames, pgavlin, swaroop.sridhar, AndyAyers Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9546 llvm-svn: 237214
* [PlaceSafepoints] Followup to commit L237172Philip Reames2015-05-121-10/+5
| | | | | | | | | Responding to review feedback from http://reviews.llvm.org/D9585 1) Remove a variable shadow by converting the outer loop to a range for loop. We never really used the 'i' variable which was being shadowed. 2) Reduce DominatorTree recalculations by passing the DT to SplitEdge. llvm-svn: 237212
* CodeGen: ignore DEBUG_VALUE nodes in KILL taggingSaleem Abdulrasool2015-05-121-0/+6
| | | | | | | DEBUG_VALUE nodes do not take part in code generation. Ignore them when performing KILL updates. Addresses PR23486. llvm-svn: 237211
* Revert r237175: [X86] Always return the sret parameter in eax/rax ...Chandler Carruth2015-05-121-15/+21
| | | | | | | This commit broke an x86 test and the bots have been broken for well over an hour now so I'm just reverting. llvm-svn: 237210
* [Unrolling] Refactor the start and step offsets to simplify overflowChandler Carruth2015-05-121-10/+26
| | | | | | | | | | | | | | | | | | checking and make the cache faster and smaller. I had thought that using an APInt here would be useful, but I think I was just wrong. Notably, we don't have to do any fancy overflow checking, we can just bound the values as quite small and do the math in a higher precision integer. I've switched to a signed integer so that UBSan will even point out if we ever have integer overflow. I've added various asserts to try to catch things as well and hoisted the overflow checks so that we just leave the too-large offsets out of the SCEV-GEP cache. This makes the value in the cache quite a bit smaller which is probably worthwhile. No functionality changed here (for trip counts under 1 billion). llvm-svn: 237209
* [lib/Fuzzer] A simple script to synchronise a fuzz test corpus with an ↵Kostya Serebryany2015-05-121-0/+17
| | | | | | external git repository. llvm-svn: 237208
* CVP: Improve handling of Selects used as incoming PHI valuesBjorn Steinbrink2015-05-121-11/+30
| | | | | | | | | | | | | | Summary: If the branch that leads to the PHI node and the Select instruction depend on correlated conditions, we might be able to directly use the corresponding value from the Select instruction as the incoming value for the PHI node, allowing later removal of the select instruction. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9051 llvm-svn: 237201
* [RewriteStatepointsForGC] Extend base pointer to handle more cases w/vectorsPhilip Reames2015-05-121-9/+36
| | | | | | | | | | When relocating a pointer, we need to determine a base pointer for the derived pointer being relocated. We have limited support for handling a pointer extracted from a vector; the current code only handled the case where the entire vector was known to contain base pointers. This patch extends the reasoning to handle chains of insertelements where the indices are constants. This case turns out to be fairly common in vectorized code. We can now handle vectors which contains mixtures of base and derived pointers provided the insertelements use constant indices. Note that this doesn't solve the general problem. To handle variable indexed insertelements, we'd need to scalarize and introduce conditional branching based on the index. Alternatively, we could eagerly scalarize, but the code structure doesn't currently make either fix easy. The patch also doesn't handle shufflevector or other vector manipulation for much the same reasons. I plan to defer this work until I have a motivating test case. Differential Revision: http://reviews.llvm.org/D9676 llvm-svn: 237200
* [lib/Fuzzer] use sha1sum for the file hashKostya Serebryany2015-05-121-0/+30
| | | | llvm-svn: 237198
* [PlaceSafepoints] Add missing "override" to ↵Justin Bogner2015-05-121-2/+2
| | | | | | | | PlaceBackedgeSafepointsImpl::runOnFunction Pointed out by -Winconsistent-missing-override. llvm-svn: 237196
* MergeFunctions: Two different sized allocas are *not* the sameArnold Schwaighofer2015-05-121-0/+9
| | | | llvm-svn: 237193
* [Statepoints] Clean up statepoint argument accessors.Pat Gavlin2015-05-121-22/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D9622 llvm-svn: 237191
* Revert "ARM: Remove Itineraries for swift CPU"Matthias Braun2015-05-121-0/+1046
| | | | | | | | Reverting until I figure out the new lit failures. This reverts commit r237179. llvm-svn: 237189
* InstrProf: Update name of compiler-rt routine for setting filenameJustin Bogner2015-05-121-1/+1
| | | | | | Patch by Teresa Johnson. llvm-svn: 237186
* [PlaceSafepoints] Switch to being a FunctionPassPhilip Reames2015-05-121-11/+6
| | | | | | | | The pass doesn't actually modify the module outside of the function being processed. The only confusing piece is that it both inserts calls and then inlines the resulting calls. Given that, it definitely invalidates module level analysis results, but many FunctionPasses do that. Differential Revision: http://reviews.llvm.org/D9590 llvm-svn: 237185
* [PlaceSafepoints] Make internal helper pass a FunctionPassPhilip Reames2015-05-121-11/+30
| | | | | | | | | | Switch from using a LoopPass to using a FunctionPass for the internal helper analysis pass. The next step is going to be to make this a true analysis pass which is required by the PlaceSafepoints pass itself. p.s. The interesting semantic part here is that we're changing the iteration order over the loops. It shouldn't matter, but that's the reason to separate this into it's own distinct patch. Differential Revision: http://reviews.llvm.org/D9588 llvm-svn: 237180
* ARM: Remove Itineraries for swift CPUMatthias Braun2015-05-121-1046/+0
| | | | | | | | | | They do more harm than good when used in the MachineScheduler as they tend to take preference to register pressure minimsation which is more important for swift. Differential Revision: http://reviews.llvm.org/D9718 llvm-svn: 237179
* [PlaceSafepoints] Use analysis infrastructure to get dominator treePhilip Reames2015-05-121-6/+4
| | | | | | | | The old code computed dominators for every loop. This was terribly slow with no good reason. Just use the standard infrastructure for analysis passes. Differential Revision: http://reviews.llvm.org/D9586 llvm-svn: 237176
* [X86] Always return the sret parameter in eax/rax, even on 32-bitReid Kleckner2015-05-121-21/+15
| | | | | | | | | | | | | | | | | | | Summary: This rule was always in the old SysV i386 ABI docs and the new ones that H.J. Lu has put together, but we never noticed: EAX scratch register; also used to return integer and pointer values from functions; also stores the address of a returned struct or union Fixes PR23491. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9715 llvm-svn: 237175
* [PlaceSafepoints] Remove dependence on LoopSimplifyPhilip Reames2015-05-121-29/+40
| | | | | | | | As a step towards getting rid of internal pass manager hack entirely, remove the need for loop simplify to run in the inner pass manager. The new code does produce slightly different loop structures, so this isn't technically NFC. Differential Revision: http://reviews.llvm.org/D9585 llvm-svn: 237172
* Convert PHI getIncomingValue() to foreach over incoming_values(). NFC.Pete Cooper2015-05-1217-49/+40
| | | | | | | | We already had a method to iterate over all the incoming values of a PHI. This just changes all eligible code to use it. Ineligible code included anything which cared about the index, or was also trying to get the i'th incoming BB. llvm-svn: 237169
* Constify method. NFCPete Cooper2015-05-121-1/+1
| | | | llvm-svn: 237167
* [Statepoints] Split the calling convention and statepoint flags operand to ↵Pat Gavlin2015-05-121-22/+15
| | | | | | | | STATEPOINT into two separate operands. Differential Revision: http://reviews.llvm.org/D9623 llvm-svn: 237166
* Strip trailing whitespace. NFCDouglas Katzman2015-05-124-5/+5
| | | | llvm-svn: 237165
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-125-76/+69
| | | | | | | | | | | | AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 llvm-svn: 237164
* [lib/Fuzzer] guess the right number of workers if -jobs=N is given but ↵Kostya Serebryany2015-05-124-1/+18
| | | | | | -workers=M is not. Update the docs. llvm-svn: 237163
* Revert r237157, "YAML: Fix typos. NFC".Alex Lorenz2015-05-121-2/+2
| | | | | | 'Iff' isn't a typo, it's a shorthand for 'if and only if'. llvm-svn: 237160
* [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructionsJozef Kolek2015-05-123-3/+36
| | | | | | | | This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
* YAML: Fix typos. NFC.Alex Lorenz2015-05-121-2/+2
| | | | llvm-svn: 237157
* Reimplement heuristic for estimating complete-unroll optimization effects.Michael Zolotukhin2015-05-121-248/+300
| | | | | | | | | | | | | | | | | | | | Summary: This patch reimplements heuristic that tries to estimate optimization beneftis from complete loop unrolling. In this patch I kept the minimal changes - e.g. I removed code handling branches and folding compares. That's a promising area, but now there are too many questions to discuss before we can enable it. Test Plan: Tests are included in the patch. Reviewers: hfinkel, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8816 llvm-svn: 237156
* [Mips] Return false for isFPCloseToIncomingSP()Petar Jovanovic2015-05-121-0/+2
| | | | | | | | | | | | | On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 llvm-svn: 237153
* R600/SI: add pass to mark CF live ranges as non-spillableTom Stellard2015-05-124-0/+110
| | | | | | | | | | | | | | | | | | | | | | Spilling can insert instructions almost anywhere, and this can mess up control flow lowering in a multitude of ways, due to instruction reordering. Let's sort this out the easy way: never spill registers involved with control flow, i.e. saved EXEC masks. Unfortunately, this does not work at all with optimizations disabled, as the register allocator ignores spill weights. This should be addressed in a future commit. The test was reduced from the "stacks" shader of [1]. Some issues trigger the machine verifier while another one is checked manually. [1] http://madebyevan.com/webgl-path-tracing/ v2: only insert pass with optimizations enabled, merge test runs. Patch by: Grigori Goronzy llvm-svn: 237152
* Changed renaming of local symbols by inserting a dot vefore the numeric suffix.Sunil Srivastava2015-05-121-1/+1
| | | | | | | One code change and several test changes to match that details in http://reviews.llvm.org/D9481 llvm-svn: 237150
* [DWARF] Add CIE header fields address_size and segment_size when generating ↵Keith Walker2015-05-122-7/+26
| | | | | | | | | | | | | dwarf-4 The DWARF-4 specification added 2 new fields in the CIE header called address_size and segment_size. Create these 2 new fields when generating dwarf-4 CIE entries, print out the new fields when dumping the CIE and update tests Differential Revision: http://reviews.llvm.org/D9558 llvm-svn: 237145
* use 'auto' to improve readability; NFCSanjay Patel2015-05-121-2/+1
| | | | llvm-svn: 237144
* R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0Tom Stellard2015-05-122-9/+4
| | | | | | | | We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but it is easier to just change the definition of SI_SPILL_S32_RESTORE to only allow numbered sgprs. llvm-svn: 237143
* R600/SI: Remove M0Reg register classTom Stellard2015-05-123-4/+1
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-126-118/+259
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
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