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* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-126-33/+59
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237140
* R600/SI: Remove explicit m0 operand from s_sendmsgTom Stellard2015-05-126-8/+36
| | | | | | | | | | | | | | | Instead add m0 as an implicit operand. This allows us to avoid using the M0Reg register class and eliminates a number of unnecessary spills when using s_sendmsg instructions. This impacts one shader in the shader-db: SGPRS: 48 -> 40 (-16.67 %) VGPRS: 112 -> 108 (-3.57 %) Code Size: 40132 -> 38796 (-3.33 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 2048 -> 0 (-100.00 %) bytes per wave llvm-svn: 237133
* R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)Tom Stellard2015-05-123-7/+11
| | | | | | | TRI->getRegClass() takes a register class ID, not a register. We were using this incorrectly in a few places. llvm-svn: 237132
* AVX-512, X86: Added lowering for shift operations for SKX.Elena Demikhovsky2015-05-121-101/+65
| | | | | | | | The other changes in the LowerShift() are not functional, just to make the code more convenient. So, the functional changes for SKX only. llvm-svn: 237129
* [ARM] Use AEABI aligned function variantsJohn Brawn2015-05-122-51/+141
| | | | | | | | | | | AEABI defines aligned variants of memcpy etc. that can be faster than the default version due to not having to do alignment checks. When emitting target code for these functions make use of these aligned variants if possible. Also convert memset to memclr if possible. Differential Revision: http://reviews.llvm.org/D8060 llvm-svn: 237127
* Reverse ordering of base and derived pointer during safepoint lowering.Igor Laevsky2015-05-121-10/+12
| | | | | | | | According to the documentation in StackMap section for the safepoint we should have: "The first Location in each pair describes the base pointer for the object. The second is the derived pointer actually being relocated." But before this change we emitted them in reverse order - derived pointer first, base pointer second. llvm-svn: 237126
* [X86] Remove useless target specific combine on TRUNCATE dag nodes.Andrea Di Biagio2015-05-121-11/+0
| | | | | | | | | | | | | Before revision 171146, function 'PerformTruncateCombine' used to perform a premature lowering of TRUNCATE dag nodes. Revision 171146 then moved all the logic implemented by PerformTruncateCombine to a custom lowering hook. However, that revision forgot to delete function PerformTruncateCombine from the code. This patch removes function 'PerformTruncateCombine' since it has no effect on the SelectionDAG. No functional change intended. llvm-svn: 237122
* [mips][FastISel] Handle calls with non legal types i8 and i16.Vasileios Kalintiris2015-05-121-1/+3
| | | | | | | | | | | | | | | | | | Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 llvm-svn: 237121
* [mips][FastISel] Allow computation of addresses from constant expressions.Vasileios Kalintiris2015-05-121-2/+4
| | | | | | | | | | | | | | | | | | | Summary: Try to compute addresses when the offset from a memory location is a constant expression. Based on a patch by Reed Kotler. Test Plan: Passes test-suite for -O0/O2 and mips 32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6767 llvm-svn: 237117
* Change TargetParser enum names to avoid macro conflicts (llvm)Renato Golin2015-05-124-123/+123
| | | | | | | | | sys/time.h on Solaris (and possibly other systems) defines "SEC" as "1" using a cpp macro. The result is that this fails to compile. Fixes https://llvm.org/PR23482 llvm-svn: 237112
* AVX-512: select operation for i1 vectorsElena Demikhovsky2015-05-122-0/+25
| | | | | | | | like: select i1 %cond, <16 x i1> %a, <16 x i1> %b. I added pseudo-CMOV patterns to resolve the "select". Added tests for KNL and SKX. llvm-svn: 237106
* [X86] DAGCombine should not assume arbitrary vector types are simpleMichael Kuperstein2015-05-121-1/+1
| | | | | | | | | The X86-specific DAGCombine for stores should not assume vector types are always simple. This fixes PR23476. Differential Revision: http://reviews.llvm.org/D9659 llvm-svn: 237097
* Remove unnecessary variables by folding calls into for loop header. NFC.Craig Topper2015-05-121-4/+2
| | | | llvm-svn: 237090
* [lib/Fuzzer] remove the -dfsan=1 flag, just use -use_traces=1 (w/ or w/o dfsan)Kostya Serebryany2015-05-125-8/+4
| | | | llvm-svn: 237083
* [lib/Fuzzer] detach the pulse thread instad of joining itKostya Serebryany2015-05-121-1/+1
| | | | llvm-svn: 237082
* Migrate existing backends that care about software floating pointEric Christopher2015-05-1218-48/+81
| | | | | | | | | | | | | | | | | | | | to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. llvm-svn: 237079
* Fixing memory leakAndrew Kaylor2015-05-121-0/+2
| | | | llvm-svn: 237072
* Refactoring gc_relocate related code in CodeGenPrepare.cppSanjoy Das2015-05-111-7/+4
| | | | | | | | | | | | | | | | | | | | Summary: The original code inserted new instructions by following a Create->Remove->ReInsert flow. This patch removes the unnecessary Remove->ReInsert part by setting up the InsertPoint correctly at the very beginning. This change does not introduce any functionality change. Patch by Chen Li! Reviewers: reames, AndyAyers, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9687 llvm-svn: 237070
* Rename variables in gc_relocate related functions to follow LLVM's naming ↵Sanjoy Das2015-05-112-47/+47
| | | | | | | | | | | | | | | | | | | | conventions. Summary: This patch is to rename some variables to CamelCase in gc_relocate related functions. There is no functionality change. Patch by Chen Li! Reviewers: reames, AndyAyers, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9681 llvm-svn: 237069
* [lib/Fuzzer] don't record traces when trace collection is offKostya Serebryany2015-05-111-1/+2
| | | | llvm-svn: 237067
* [MemCpyOpt] Look at any dependency -not just source- for memset+memcpy.Ahmed Bougacha2015-05-111-6/+7
| | | | | | | | | | This fixes another miscompile introduced by r235232: when there was a dependency on the memcpy destination other than the memset, we would ignore it, because we only looked at the source dependency. It was a mistake to use SrcDepInfo. Instead, just use DepInfo. llvm-svn: 237066
* Simplify a return expression and an access to an alloca's allocated typeDavid Blaikie2015-05-111-3/+3
| | | | llvm-svn: 237065
* [WinEH] Handle nested landing pads that return directly to the parent function.Andrew Kaylor2015-05-111-10/+104
| | | | | | Differential Revision: http://reviews.llvm.org/D9684 llvm-svn: 237063
* Readdress r236990, use of static members on a non-static variable.David Blaikie2015-05-113-46/+35
| | | | | | | | | | | | The TargetRegistry is just a namespace-like class, instantiated in one place to use a range-based for loop. Instead, expose access to the registry via a range-based 'targets()' function instead. This makes most uses a bit awkward/more verbose - but eventually we should just add a range-based find_if function which will streamline these functions. I'm happy to mkae them a bit awkward in the interim as encouragement to improve the algorithms in time. llvm-svn: 237059
* Fix tablegen's PrintFatalError function to run registered fileJames Y Knight2015-05-111-0/+5
| | | | | | | | | | | | | | | cleanups. Also, change code in tablegen which printed a message and then called "exit(1)" to use PrintFatalError, instead. This fixes instances where an empty output file was left behind after a failed tablegen invocation, which would confuse subsequent ninja runs into not attempting to rebuild. Differential Revision: http://reviews.llvm.org/D9608 llvm-svn: 237058
* [lib/Fuzzer] when running multiple fuzzing processes, print something every ↵Kostya Serebryany2015-05-111-2/+14
| | | | | | 10 minutes to avoid buildbot timeouts llvm-svn: 237054
* [lib/Fuzzer] rename FuzzerDFSan.cpp to FuzzerTraceState.cpp; update ↵Kostya Serebryany2015-05-114-44/+54
| | | | | | comments. NFC expected llvm-svn: 237050
* propagate IR-level fast-math-flags to DAG nodes; 2nd try; NFCSanjay Patel2015-05-114-52/+56
| | | | | | | | | | | | | | | | | | | | | | | This is a less ambitious version of: http://reviews.llvm.org/rL236546 because that was reverted in: http://reviews.llvm.org/rL236600 because it caused memory corruption that wasn't related to FMF but was actually due to making nodes with 2 operands derive from a plain SDNode rather than a BinarySDNode. This patch adds the minimum plumbing necessary to use IR-level fast-math-flags (FMF) in the backend without actually using them for anything yet. This is a follow-on to: http://reviews.llvm.org/rL235997 ...which split the existing nsw / nuw / exact flags and FMF into their own struct. llvm-svn: 237046
* [LoopIdiomRecognize] Transform backedge-taken count check into an assertion.Davide Italiano2015-05-111-1/+3
| | | | | | | | | runOnCountable() allowed the caller to call on a loop without a predictable backedge-taken count. Change the code so that only loops with computable backdge-count can call this function, in order to catch abuses. llvm-svn: 237044
* [lib/Fuzzer] add a trace-based mutatation logic. Same idea as with ↵Kostya Serebryany2015-05-115-12/+68
| | | | | | DFSan-based mutator, but instead of relying on taint tracking, try to find the data directly in the input. More (logic and comments) to go. llvm-svn: 237043
* Fixing build warningsAndrew Kaylor2015-05-111-2/+2
| | | | llvm-svn: 237042
* [WinEH] Update exception numbering to give handlers their own base state.Andrew Kaylor2015-05-112-16/+87
| | | | | | Differential Revision: http://reviews.llvm.org/D9512 llvm-svn: 237014
* [RewriteStatepointsForGC] Fix a bug on creating gc_relocate for pointer to ↵Sanjoy Das2015-05-114-14/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vector of pointers Summary: In RewriteStatepointsForGC pass, we create a gc_relocate intrinsic for each relocated pointer, and the gc_relocate has the same type with the pointer. During the creation of gc_relocate intrinsic, llvm requires to mangle its type. However, llvm does not support mangling of all possible types. RewriteStatepointsForGC will hit an assertion failure when it tries to create a gc_relocate for pointer to vector of pointers because mangling for vector of pointers is not supported. This patch changes the way RewriteStatepointsForGC pass creates gc_relocate. For each relocated pointer, we erase the type of pointers and create an unified gc_relocate of type i8 addrspace(1)*. Then a bitcast is inserted to convert the gc_relocate to the correct type. In this way, gc_relocate does not need to deal with different types of pointers and the unsupported type mangling is no longer a problem. This change would also ease further merge when LLVM erases types of pointers and introduces an unified pointer type. Some minor changes are also introduced to gc_relocate related part in InstCombineCalls, CodeGenPrepare, and Verifier accordingly. Patch by Chen Li! Reviewers: reames, AndyAyers, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9592 llvm-svn: 237009
* LiveRangeCalc: Improve error messages on malformed IRMatthias Braun2015-05-111-1/+7
| | | | llvm-svn: 237008
* [X86] Updates to X86 backend for f16 promotionPirama Arumuga Nainar2015-05-111-0/+22
| | | | | | | | | | | | | | | | | | | | | | | Summary: r235215 adds support for f16 to be considered as a load/store type and promote f16 operations to f32. This patch has miscellaneous fixes for the X86 backend so all f16 operations are handled: 1. Set loadextaction for f16 vectors to expand. 2. Handle FP_EXTEND in a switch statement when handling v2f32 3. Do not fold (FP_TO_SINT (load f16)) into FP_TO_INT*_IN_MEM or (store (SINT_TO_FP )) to a FILD. Tests included. Reviewers: ab, srhines, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9092 llvm-svn: 237004
* Rip min/max pattern matching out of InstCombine and intoJames Molloy2015-05-113-99/+85
| | | | | | | | | | | ValueTracking. This matching functionality is useful in more than just InstCombine, so make it available in ValueTracking. NFC. llvm-svn: 236998
* Silencing an MSVC warning: '<<' : result of 32-bit shift implicitly ↵Aaron Ballman2015-05-111-1/+1
| | | | | | converted to 64 bits (was 64-bit shift intended?); NFC llvm-svn: 236987
* AVX-512: Changed CC parameter in "cmp" intrinsicElena Demikhovsky2015-05-111-89/+0
| | | | | | | | from i8 to i32 according to the Intel Spec by Igor Breger (igor.breger@intel.com) llvm-svn: 236979
* [InstCombine/PowerPC] Fix single-precision QPX load/store replacementHal Finkel2015-05-111-5/+10
| | | | | | | | | | The QPX single-precision load/store intrinsics have implied truncation/extension from/to the declared value type of <4 x double> to the memory type of <4 x float>. When we can prove the alignment of the pointer argument, and thus replace the intrinsic with a regular load or store, we need to load or store the correct data type (<4 x float>) instead of (<4 x double>). llvm-svn: 236973
* Fixed compilation warning, NFC.Elena Demikhovsky2015-05-111-0/+2
| | | | llvm-svn: 236972
* AVX-512: Added SKX instructions and intrinsics:Elena Demikhovsky2015-05-114-70/+101
| | | | | | | | {add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 236971
* [InstCombine] Canonicalize single element array storeDavid Majnemer2015-05-111-0/+9
| | | | | | | | Use the element type instead of the aggregate type. Differential Revision: http://reviews.llvm.org/D9591 llvm-svn: 236969
* [InstCombine] Canonicalize single element array loadDavid Majnemer2015-05-111-0/+10
| | | | | | | | Use the element type instead of the aggregate type. Differential Revision: http://reviews.llvm.org/D9596 llvm-svn: 236968
* AVX-512: fixed UINT_TO_FP operation for 512-bit types.Elena Demikhovsky2015-05-101-0/+7
| | | | llvm-svn: 236955
* [SelectionDAG] Fixed constant folding issue when legalised types are smaller ↵Simon Pilgrim2015-05-101-2/+3
| | | | | | | | then the folded type. Found when testing with llvm-stress on i686 targets. llvm-svn: 236954
* SanitizerCoverage: Use `createSanitizerCtor` to create ctor and call initIsmail Pazarbasi2015-05-101-20/+13
| | | | | | | | | | | | | | Second attempt; instead of using a named local variable, passing arguments directly to `createSanitizerCtorAndInitFunctions` worked on Windows. Reviewers: kcc, samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8780 llvm-svn: 236951
* AVX-512: fixed a bug in i1 vectors loweringElena Demikhovsky2015-05-102-2/+12
| | | | llvm-svn: 236947
* SystemZ: silence a GCC warningSaleem Abdulrasool2015-05-101-2/+2
| | | | | | | | warning: enumeral and non-enumeral type in conditional expression Cast the 0 to the appropriate type. NFC. Identified by GCC 4.9.2 llvm-svn: 236942
* Fix MergeConsecutiveStore for non-byte-sized memory accesses.James Y Knight2015-05-091-0/+4
| | | | | | | | | | | | | | | | | | | The bug showed up as a compile-time assertion failure: Assertion `NumBits >= MIN_INT_BITS && "bitwidth too small"' failed when building msan tests on x86-64. Prior to r236850, this bug was masked due to a bogus alignment check, which also accidentally rejected non-byte-sized accesses. Afterwards, an invalid ElementSizeBytes == 0 got further into the function, and triggered the assertion failure. It would probably be a good idea to allow it to handle merging stores of unusual widths as well, but for now, to un-break it, I'm just making the minimal fix. Differential Revision: http://reviews.llvm.org/D9626 llvm-svn: 236927
* MachineCSE: Add a target query for the LookAheadLimit heurisiticTom Stellard2015-05-092-2/+5
| | | | | | | | | This is used to determine whether or not to CSE physical register defs. Differential Revision: http://reviews.llvm.org/D9472 llvm-svn: 236923
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