summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* regenerateChris Lattner2005-11-061-820/+775
| | | | llvm-svn: 24208
* factor optional alignmentChris Lattner2005-11-061-34/+23
| | | | llvm-svn: 24207
* ask for 16-byte aligned jmpbufs. This should unbreak C++ on IA64 (andDuraid Madina2005-11-061-1/+2
| | | | | | | a bunch of other things) but is currently ignored by the code generator. llvm-svn: 24206
* Write/read allocation instruction alignment info to .bc files.Chris Lattner2005-11-052-8/+21
| | | | llvm-svn: 24203
* verify that alignments are always a power of 2Chris Lattner2005-11-051-0/+2
| | | | llvm-svn: 24200
* regenerateChris Lattner2005-11-051-164/+176
| | | | llvm-svn: 24199
* Verify that alignment amounts are a power of 2Chris Lattner2005-11-051-0/+12
| | | | llvm-svn: 24198
* fix printing the alignment directiveChris Lattner2005-11-051-1/+1
| | | | llvm-svn: 24197
* Add support alignment of allocation instructions.Nate Begeman2005-11-0511-3285/+2650
| | | | | | | | | Add support for specifying alignment and size of setjmp jmpbufs. No targets currently do anything with this information, nor is it presrved in the bytecode representation. That's coming up next. llvm-svn: 24196
* add a case Nate sent meChris Lattner2005-11-051-0/+23
| | | | llvm-svn: 24195
* Implement Transforms/TailCallElim/return-undef.ll, a trivial caseChris Lattner2005-11-051-0/+1
| | | | | | that has been sitting in my inbox since May 18. :) llvm-svn: 24194
* Turn sdiv into udiv if both operands have a clear sign bit. This occursChris Lattner2005-11-051-0/+19
| | | | | | | | | | | | | | | | | a few times in crafty: OLD: %tmp.36 = div int %tmp.35, 8 ; <int> [#uses=1] NEW: %tmp.36 = div uint %tmp.35, 8 ; <uint> [#uses=0] OLD: %tmp.19 = div int %tmp.18, 8 ; <int> [#uses=1] NEW: %tmp.19 = div uint %tmp.18, 8 ; <uint> [#uses=0] OLD: %tmp.117 = div int %tmp.116, 8 ; <int> [#uses=1] NEW: %tmp.117 = div uint %tmp.116, 8 ; <uint> [#uses=0] OLD: %tmp.92 = div int %tmp.91, 8 ; <int> [#uses=1] NEW: %tmp.92 = div uint %tmp.91, 8 ; <uint> [#uses=0] Which all turn into shrs. llvm-svn: 24190
* Turn srem -> urem when neither input has their sign bit set. This triggersChris Lattner2005-11-051-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | 8 times in vortex, allowing the srems to be turned into shrs: OLD: %tmp.104 = rem int %tmp.5.i37, 16 ; <int> [#uses=1] NEW: %tmp.104 = rem uint %tmp.5.i37, 16 ; <uint> [#uses=0] OLD: %tmp.98 = rem int %tmp.5.i24, 16 ; <int> [#uses=1] NEW: %tmp.98 = rem uint %tmp.5.i24, 16 ; <uint> [#uses=0] OLD: %tmp.91 = rem int %tmp.5.i19, 8 ; <int> [#uses=1] NEW: %tmp.91 = rem uint %tmp.5.i19, 8 ; <uint> [#uses=0] OLD: %tmp.88 = rem int %tmp.5.i14, 8 ; <int> [#uses=1] NEW: %tmp.88 = rem uint %tmp.5.i14, 8 ; <uint> [#uses=0] OLD: %tmp.85 = rem int %tmp.5.i9, 1024 ; <int> [#uses=2] NEW: %tmp.85 = rem uint %tmp.5.i9, 1024 ; <uint> [#uses=0] OLD: %tmp.82 = rem int %tmp.5.i, 512 ; <int> [#uses=2] NEW: %tmp.82 = rem uint %tmp.5.i1, 512 ; <uint> [#uses=0] OLD: %tmp.48.i = rem int %tmp.5.i.i161, 4 ; <int> [#uses=1] NEW: %tmp.48.i = rem uint %tmp.5.i.i161, 4 ; <uint> [#uses=0] OLD: %tmp.20.i2 = rem int %tmp.5.i.i, 4 ; <int> [#uses=1] NEW: %tmp.20.i2 = rem uint %tmp.5.i.i, 4 ; <uint> [#uses=0] it also occurs 9 times in gcc, but with odd constant divisors (1009 and 61) so the payoff isn't as great. llvm-svn: 24189
* Fix logic bug in finding retry slot in tally.Jim Laskey2005-11-051-15/+33
| | | | llvm-svn: 24188
* Fix a warningJim Laskey2005-11-041-0/+1
| | | | llvm-svn: 24187
* oops, forgot to load GP for indirect calls, though the old code now commentedDuraid Madina2005-11-041-4/+21
| | | | | | | | | out failed (e.g. methcall) - now the code compiles, though it's not quite right just yet (tm) ;) would fix this but it's 3am! :O llvm-svn: 24186
* kill redundant SP/GP/RP save/restores across callsDuraid Madina2005-11-041-2/+3
| | | | llvm-svn: 24183
* add support for loading boolsDuraid Madina2005-11-041-1/+7
| | | | llvm-svn: 24182
* Scheduling now uses itinerary data.Jim Laskey2005-11-041-166/+201
| | | | llvm-svn: 24180
* fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1)Duraid Madina2005-11-041-41/+97
| | | | llvm-svn: 24175
* add pattern to load constant 0 into a predicate regDuraid Madina2005-11-031-0/+2
| | | | llvm-svn: 24164
* Fix a bug that prevented this pattern from matchingChris Lattner2005-11-031-1/+1
| | | | llvm-svn: 24161
* Fix a crash that Andrew noticed, and add a pair of braces to unfconfuseNate Begeman2005-11-021-5/+5
| | | | | | XCode's indenting. llvm-svn: 24159
* make this 64 bit clean, fixed test30 of ↵Andrew Lenharth2005-11-021-1/+1
| | | | | | /Regression/Transforms/InstCombine/add.ll llvm-svn: 24158
* Fix a QOI issue noticed by Markus F.X.J. Oberhumer.Chris Lattner2005-11-021-0/+1
| | | | | | This fixes PR641 llvm-svn: 24154
* "fix" support for FP constants (this code asserts in the scheduler,Duraid Madina2005-11-021-2/+4
| | | | | | though) llvm-svn: 24152
* add F0 and F1 to the FP register classDuraid Madina2005-11-021-3/+19
| | | | llvm-svn: 24151
* This works nowChris Lattner2005-11-021-2/+1
| | | | llvm-svn: 24150
* add support for SELECT to TargetSelectionDAG.td, add support forDuraid Madina2005-11-022-31/+43
| | | | | | selecting ints to IA64, and a few other ia64 bits and pieces llvm-svn: 24147
* add support for loading FP constants +0.0 and +1.0 to the dag isel,Duraid Madina2005-11-022-3/+8
| | | | | | stop pretending -0.0 and -1.0 are machine constants llvm-svn: 24146
* Fix a source of undefined behavior when dealing with 64-bit types. ThisChris Lattner2005-11-021-1/+1
| | | | | | may fix PR652. Thanks to Andrew for tracking down the problem. llvm-svn: 24145
* Allow itineraries to be passed through the Target Machine.Jim Laskey2005-11-014-5/+21
| | | | llvm-svn: 24139
* heh, scheduling was easy?Duraid Madina2005-11-011-1/+3
| | | | | | need to send chris, jim and sampo a box of fish each llvm-svn: 24135
* FORTRAN!!! :( and other similarly unfortunate things mean that on ia64Duraid Madina2005-11-011-0/+20
| | | | | | one sometimes needs to pass FP args in both FP *and* integer registers. llvm-svn: 24134
* so tablegen was thinking I might want to convert FPs to predicates.Duraid Madina2005-11-011-4/+3
| | | | | | clever little tablegen! llvm-svn: 24133
* add support for int->FP and FP->int ops, and add ia64 patterns for theseDuraid Madina2005-11-012-0/+23
| | | | llvm-svn: 24132
* add zeroextend predicate->integerDuraid Madina2005-11-011-37/+42
| | | | llvm-svn: 24131
* Add a flag to enable a darwin linker optimizationChris Lattner2005-11-011-1/+7
| | | | llvm-svn: 24130
* Make constant pool entries use private labels. This is important when you'reChris Lattner2005-10-311-3/+3
| | | | | | not compiling a whole program at a time :) llvm-svn: 24129
* Fix an iterator invalidation problem in code used by the -strip passChris Lattner2005-10-311-1/+1
| | | | llvm-svn: 24124
* Limit the search depth of MaskedValueIsZero to 6 instructions, to avoidChris Lattner2005-10-311-10/+14
| | | | | | | bad cases. This fixes Markus's second testcase in PR639, and should seal it for good. llvm-svn: 24123
* 1. Embed and not inherit vector for NodeGroup.Jim Laskey2005-10-311-20/+39
| | | | | | | | 2. Iterate operands and not uses (performance.) 3. Some long pending comment changes. llvm-svn: 24119
* add FP compares and implicit register defs to the dag iselDuraid Madina2005-10-312-23/+45
| | | | llvm-svn: 24118
* Significantly simplify this code and make it more aggressive. Instead of havingChris Lattner2005-10-301-103/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a special case hack for X86, make the hack more general: if an incoming argument register is not used in any block other than the entry block, don't copy it to a vreg. This helps us compile code like this: %struct.foo = type { int, int, [0 x ubyte] } int %test(%struct.foo* %X) { %tmp1 = getelementptr %struct.foo* %X, int 0, uint 2, int 100 %tmp = load ubyte* %tmp1 ; <ubyte> [#uses=1] %tmp2 = cast ubyte %tmp to int ; <int> [#uses=1] ret int %tmp2 } to: _test: lbz r3, 108(r3) blr instead of: _test: lbz r2, 108(r3) or r3, r2, r2 blr The (dead) copy emitted to copy r3 into a vreg for extra-block uses was increasing the live range of r3 past the load, preventing the coallescing. This implements CodeGen/PowerPC/reg-coallesce-simple.ll llvm-svn: 24115
* Reduce the number of copies emitted as machine instructions byChris Lattner2005-10-301-16/+57
| | | | | | | | | | | | | | | | | generating results in vregs that will need them. In the case of something like this: CopyToReg((add X, Y), reg1024), we no longer emit code like this: reg1025 = add X, Y reg1024 = reg 1025 Instead, we emit: reg1024 = add X, Y Whoa! :) llvm-svn: 24111
* If the module has no t-t and the host is an alpha, default to using the Alpha BEChris Lattner2005-10-301-1/+1
| | | | llvm-svn: 24110
* fix some broken comparisons, this affected the Pattern isel too.Duraid Madina2005-10-301-27/+4
| | | | llvm-svn: 24109
* This is implementedChris Lattner2005-10-301-19/+0
| | | | llvm-svn: 24107
* Codegen mul by negative power of two with a shift and negate.Chris Lattner2005-10-301-3/+13
| | | | | | | | | | | | | | | | | | | This implements test/Regression/CodeGen/PowerPC/mul-neg-power-2.ll, producing: _foo: slwi r2, r3, 1 subfic r3, r2, 63 blr instead of: _foo: mulli r2, r3, -2 addi r3, r2, 63 blr llvm-svn: 24106
* Fix a problem that Nate noticed with LSR:Chris Lattner2005-10-301-1/+26
| | | | | | | | | | | | | | | | | | | | When inserting code for an addrec expression with a non-unit stride, be more careful where we insert the multiply. In particular, insert the multiply in the outermost loop we can, instead of the requested insertion point. This allows LSR to notice the mul in the right loop, reducing it when it gets to it. This allows it to reduce the multiply, where before it missed it. This happens quite a bit in the test suite, for example, eliminating 2 multiplies in art, 3 in ammp, 4 in apsi, reducing from 1050 multiplies to 910 muls in galgel (!), from 877 to 859 in applu, and 36 to 30 in bzip2. This speeds up galgel from 16.45s to 16.01s, applu from 14.21 to 13.94s and fourinarow from 66.67s to 63.48s. This implements Transforms/LoopStrengthReduce/nested-reduce.ll llvm-svn: 24102
OpenPOWER on IntegriCloud