|  | Commit message (Collapse) | Author | Age | Files | Lines | 
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| | the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.
llvm-svn: 163124 | 
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| | llvm-svn: 163123 | 
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| | MCTargetAsmParser class.
llvm-svn: 163122 | 
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| | llvm-svn: 163117 | 
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| | llvm-svn: 163116 | 
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| | No functionality change.
llvm-svn: 163115 | 
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| | Fixs PR13719.
llvm-svn: 163107 | 
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| | This code used to only handle malloc-like calls, which do not read memory.
r158919 changed it to check isNoAliasFn(), which includes strdup-like and
realloc-like calls, but it was not checking for dependencies on the memory
read by those calls.
llvm-svn: 163106 | 
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| | llvm-svn: 163104 | 
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| | llvm-svn: 163103 | 
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| | MatchInstructionImpl() function.
These values are used by the ConvertToMCInst() function to index into the
ConversionTable.  The values are also needed to call the GetMCInstOperandNum()
function.
llvm-svn: 163101 | 
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| | llvm-svn: 163100 | 
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| | llvm-svn: 163094 | 
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| | For example, the ARM target does not have efficient ISel handling for vector
selects with scalar conditions. This patch adds a TLI hook which allows the
different targets to report which selects are supported well and which selects
should be converted to CF duting codegen prepare.
llvm-svn: 163093 | 
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| | We update until we hit a fixpoint. This is probably slow but also
slightly simplifies the code. It should also fix the occasional
invalid domtrees observed when building with expensive checking.
I couldn't find a case where this had a measurable slowdown, but
if someone finds a pathological case where it does we may have
to find a cleverer way of updating dominators here.
Thanks to Duncan for the test case.
llvm-svn: 163091 | 
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| | Most of the code guarded with ANDROIDEABI are not
ARM-specific, and having no relation with arm-eabi.
Thus, it will be more natural to call this
environment "Android" instead of "ANDROIDEABI".
Note: We are not using ANDROID because several projects
are using "-DANDROID" as the conditional compilation
flag.
llvm-svn: 163087 | 
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| | not sign-extend.
llvm-svn: 163086 | 
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| | zeros or all ones.  A vector bool with just ones isn't suitable for masking with.
No test case unfortunately as i couldn't find a target which fit all
the conditions needed to hit this code.
llvm-svn: 163075 | 
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| | NEON domain conversion was too heavy-handed with its widened
registers, which could have stripped existing instructions of their
dependency, leaving them vulnerable to scheduling errors.
llvm-svn: 163070 | 
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| | vector from i1 to some other type.  rdar://problem/12210060"
This reverts commit 5dd9e214fb92847e947f9edab170f9b4e52b908f.
Thanks to Duncan for explaining how this should have been done.
Conflicts:
	test/CodeGen/X86/vec_select.ll
llvm-svn: 163064 | 
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| | llvm-svn: 163063 | 
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| | llvm-svn: 163059 | 
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| | llvm-svn: 163058 | 
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| | llvm-svn: 163053 | 
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| | fast-math mode.
llvm-svn: 163051 | 
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| | llvm-svn: 163049 | 
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| | output chain is correctly setup.
As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.
rdar://11457792
llvm-svn: 163036 | 
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| | llvm-svn: 163035 | 
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| | function nowadays.
llvm-svn: 163030 | 
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| | llvm-svn: 163029 | 
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| | Manage tied operands entirely internally to MachineInstr. This makes it
possible to change the representation of tied operands, as I will do
shortly.
The constraint that tied uses and defs must be in the same order was too
restrictive.
llvm-svn: 163021 | 
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| | - In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as
  well as PSHUFB will zero elements with negative indices.
  Patch by Sriram Murali <sriram.murali@intel.com>
llvm-svn: 163018 | 
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| | on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
llvm-svn: 163010 | 
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| | llvm-svn: 163008 | 
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| | llvm-svn: 163005 | 
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| | Match_ConversionFail enum.
llvm-svn: 163002 | 
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| | part can be commuted.
llvm-svn: 163001 | 
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| | code tolerant of instructions with more than two input operands.
llvm-svn: 163000 | 
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| | llvm-svn: 162999 | 
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| | I was too optimistic, inline asm can have tied operands that don't
follow the def order.
Fixes PR13742.
llvm-svn: 162998 | 
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| | - Overloading operator<< for raw_ostream and pointers is dangerous, it alters
  the behavior of code that includes the header.
- Remove unused ID.
- Use LLVM's byte swapping helpers instead of a hand-coded.
- Make ReadProfilingData work directly on a pointer.
No functionality change.
llvm-svn: 162992 | 
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| | llvm-svn: 162979 | 
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| | llvm-svn: 162973 | 
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| | Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.
rdar://problem/12203728
llvm-svn: 162968 | 
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| | The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.
llvm-svn: 162963 | 
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| | the ConvertToMCInst() return void, rather then a bool.  Update all the cvt
functions as well.
llvm-svn: 162961 | 
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| | i1 to some other type.  rdar://problem/12210060
llvm-svn: 162960 | 
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| | constants.  This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants.
llvm-svn: 162956 | 
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| | llvm-svn: 162955 | 
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| | belongs.
llvm-svn: 162954 |