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* Remove the unnecessary virtual dtor from the DIEUnit hierarchy (in favor of ↵David Blaikie2017-04-222-4/+4
| | | | | | | | | protected dtor in the base, final derived classes with public non-virtual dtors) These objects are never polymorphically owned/destroyed, so the virtual dtor was unnecessary. llvm-svn: 301068
* LowerSwitch: Fix producing invalid IR on unreachable codeMatt Arsenault2017-04-211-0/+8
| | | | | | | | If a switch was in an unreachable block that branched to a block with a phi, it would leave phis with missing predecessors. llvm-svn: 301064
* Move Split DWARF handling to an MC option/command line argument rather than ↵David Blaikie2017-04-211-15/+4
| | | | | | | | | | | | | | | | | | | using metadata Since Split DWARF needs to name the actual .dwo file that is generated, it can't be known at the time the llvm::Module is produced as it may be merged with other Modules before the object is generated and that object may be generated with any name. By passing the Split DWARF file name when LLVM is producing object code the .dwo file name in the object file can match correctly. The support for Split DWARF for implicit modules remains the same - using metadata to store the dwo name and dwo id so that potentially multiple skeleton CUs referring to different dwo files can be generated from one llvm::Module. llvm-svn: 301062
* Fixup for r301054: Use an explicit constructor.Kuba Mracek2017-04-211-1/+1
| | | | llvm-svn: 301061
* Remove a repeated comment line. NFC.Easwaran Raman2017-04-211-1/+0
| | | | llvm-svn: 301059
* Fixup for r301054: Only use __attribute__((no_sanitize("memory"))) when it's ↵Kuba Mracek2017-04-211-1/+5
| | | | | | available. llvm-svn: 301058
* AArch64FrameLowering: Check if the ExtraCSSpill register is actually unusedMatthias Braun2017-04-211-6/+6
| | | | | | | | | | | The code assumed that when saving an additional CSR register (ExtraCSSpill==true) we would have a free register throughout the function. This was not true if this CSR register is also used to pass values as in the swiftself case. rdar://31451816 llvm-svn: 301057
* [libFuzzer] Always build libFuzzer Kuba Mracek2017-04-211-34/+40
| | | | | | | | | | | | | | | There are two reasons why users might want to build libfuzzer: - To fuzz LLVM itself - To get the libFuzzer.a archive file, so that they can attach it to their code This change always builds libfuzzer, and supports the second use case if the specified flag is set. The point of this patch is to have something that can potentially be shipped with the compiler, and this also ensures that the version of libFuzzer is correct to use with that compiler. Patch by George Karpenkov. Differential Revision: https://reviews.llvm.org/D32096 llvm-svn: 301054
* [Object] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-04-213-114/+135
| | | | | | other minor fixes (NFC). llvm-svn: 301049
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-2116-35/+32
| | | | | | | | | In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
* [Test commit] Remove extra newline.Frederich Munch2017-04-211-1/+0
| | | | llvm-svn: 301046
* InferAddressSpaces: Infer for just GEPsMatt Arsenault2017-04-211-3/+7
| | | | | | | | | | | Fixes leaving intermediate flat addressing computations where a GEP instruction's source is a constant expression. Still leaves behind a trivial addrspacecast + gep pair that instcombine is able to handle, which ideally could be folded here directly. llvm-svn: 301044
* [PartialInliner] Partial inliner needs to check use kind before transformationXinliang David Li2017-04-211-0/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D32373 llvm-svn: 301042
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-2116-31/+35
| | | | | | This broke almost all bots. Reverting while fixing. llvm-svn: 301041
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-2116-35/+31
| | | | | | | | | | | | | | | | | | Empty functions can lead to duplicate entries in the Guard CF Function Table of a binary due to multiple functions sharing the same RVA, causing the kernel to refuse to load that binary. We had a terrific bug due to this in Chromium. It turns out we were already doing this for Mach-O in certain situations. This patch expands the code for that in AsmPrinter::EmitFunctionBody() and renames TargetInstrInfo::getNoopForMachoTarget() to simply getNoop() since it seems it was used for not just Mach-O anyway. Differential Revision: https://reviews.llvm.org/D32330 llvm-svn: 301040
* ARM: make sure we use all entries in a vector before forming a vpaddl.Tim Northover2017-04-211-5/+5
| | | | | | | | | Otherwise there's some mismatch, and we'll either form an illegal type or an illegal node. Thanks to Eli Friedman for pointing out the problem with my original solution. llvm-svn: 301036
* [InstCombine] revert r300977 and r301021Sanjay Patel2017-04-211-14/+4
| | | | | | This can cause an inf-loop. Investigating... llvm-svn: 301035
* typoAdrian Prantl2017-04-211-1/+1
| | | | llvm-svn: 301030
* AMDGPU/GFX9: Enable FastFMAF32Konstantin Zhuravlyov2017-04-211-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D32363 llvm-svn: 301029
* AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)Konstantin Zhuravlyov2017-04-211-0/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D32361 llvm-svn: 301028
* AMDGPU: Fix S_PACK_HH_B32_B16Konstantin Zhuravlyov2017-04-211-1/+1
| | | | | | | | - We really ought to zero out lower 16 bits Differential Revision: https://reviews.llvm.org/D32356 llvm-svn: 301026
* [AMDGPU] Handle SI_MASKED_UNREACHABLE in instruction emitterYaxun Liu2017-04-211-0/+6
| | | | | | | | | | | | SI_MASKED_UNREACHABLE does not have machine instruction encoding. It needs special handling in AMDGPUAsmPrinter::EmitInstruction like some other pseudo instructions. This patch fixes compilation failure of RadeonRays. Differential Revision: https://reviews.llvm.org/D32364 llvm-svn: 301025
* Revert "X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC"Matthias Braun2017-04-213-23/+34
| | | | | | | | | | | It seems we have on situation in a sanitizer enable bootstrap build where the return instruction has a frame index operand that does not point to a fixed object and fails the assert added here. This reverts commit r300923. This reverts commit r300922. llvm-svn: 301024
* AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormalsKonstantin Zhuravlyov2017-04-211-2/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D32085 llvm-svn: 301023
* [InstCombine] use isSubsetOf() for efficiencySanjay Patel2017-04-211-1/+1
| | | | | | | | | | C | ~D == -1 ~(C | ~D) == 0 ~C & D == 0 D & ~C == 0 D.isSubsetOf(C) llvm-svn: 301021
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-217-37/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300932 and r300930, which was causing dag-combine to loop forever. The problem was that optimizeLogicalImm was returning true even when there was no change to the immediate node (which happened when the immediate was all zeros or ones), which caused dag-combine to push and pop the same node to the work list over and over again without making any progress. This commit fixes the bug by returning false early in optimizeLogicalImm if the immediate is all zeros or ones. Also, it changes the code to compare the immediate with 0 or Mask rather than calling countPopulation. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 301019
* [InstCombine] fadd double (sitofp x), y check that the promotion is validArtur Pilipenko2017-04-211-22/+38
| | | | | | | | | | | | | | | Doing these transformations check that the result of integer addition is representable in the FP type. (fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst)) (fadd double (sitofp x), (sitofp y)) --> (sitofp (add int x, y)) This is a fix for https://bugs.llvm.org//show_bug.cgi?id=27036 Reviewed By: andrew.w.kaylor, scanon, spatel Differential Revision: https://reviews.llvm.org/D31182 llvm-svn: 301018
* Fixup for r301007: Restrict the -D hack to Darwin.Kuba Mracek2017-04-211-7/+9
| | | | llvm-svn: 301017
* Revert r301010: Bot failures on Windows, NetBSD and even some old Darwin.Kuba Mracek2017-04-211-20/+14
| | | | llvm-svn: 301012
* [libFuzzer] Always build libFuzzerKuba Mracek2017-04-211-14/+20
| | | | | | | | | | | | | | | There are two reasons why users might want to build libfuzzer: - To fuzz LLVM itself - To get the libFuzzer.a archive file, so that they can attach it to their code This change always builds libfuzzer, and supports the second use case if the specified flag is set. The point of this patch is to have something that can potentially be shipped with the compiler, and this also ensures that the version of libFuzzer is correct to use with that compiler. Patch by George Karpenkov. Differential Revision: https://reviews.llvm.org/D32096 llvm-svn: 301010
* [libFuzzer] Changing thread_local to __thread in libFuzzerKuba Mracek2017-04-211-0/+13
| | | | | | | | Old Apple compilers do not support thread_local keyword. This patch adds -Dthread_local=__thread when the compiler doesn't support thread_local. Differential Revision: https://reviews.llvm.org/D32312 llvm-svn: 301007
* [AArch64] Refactor instruction selection lowering for addresses. NFCIJoel Jones2017-04-212-85/+91
| | | | | | | | | | | | Factor out the common code used for generating addresses into common templated functions that call overloaded versions of a new function, getTargetNode. Tested with make check-llvm with targets AArch64. Differential Revision: https://reviews.llvm.org/D32169 llvm-svn: 301005
* ARM: don't try to create an i8 -> i32 vpaddl.Tim Northover2017-04-211-2/+5
| | | | | | | | DAG combine was mistakenly assuming that the step-up it was looking at was always a doubling, but it can sometimes be a larger extension in which case we'd crash. llvm-svn: 301002
* [libFuzzer] Check for target(popcnt) capability before usageKuba Mracek2017-04-211-2/+10
| | | | | | | | | | | Older compilers (e.g. LLVM 3.4) do not support the attribute target("popcnt"). In order to support those, this diff check the attribute support using the preprocessor. Patch by George Karpenkov. Differential Revision: https://reviews.llvm.org/D32311 llvm-svn: 300999
* [ValueTracking] Use APInt::setAllBits and APInt::intersects to simplify some ↵Craig Topper2017-04-211-3/+4
| | | | | | code. NFC llvm-svn: 300997
* [APInt] Add compare/compareSigned methods that return -1, 0, 1. Reimplement ↵Craig Topper2017-04-211-35/+9
| | | | | | | | | | | | | | | | slt/ult and friends using them Currently sle and ule have to call slt/ult and eq to get the proper answer. This results in extra code for both calls and additional scans of multiword APInts. This patch replaces slt/ult with a compareSigned/compare that can return -1, 0, or 1 so we can cover all the comparison functions with a single call. While I was there I removed the activeBits calls and other checks at the start of the slow part of ult. Both of the activeBits calls potentially scan through each of the APInts separately. I can't imagine that's any better than just scanning them in parallel and doing the compares. Now we just share the code with tcCompare. These changes seem to be good for about a 7-8k reduction on the size of the opt binary on my local x86-64 build. Differential Revision: https://reviews.llvm.org/D32339 llvm-svn: 300995
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-214-9/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
* [SimplifyCFG] Fix the determination of PostBB in conditional store merging ↵Craig Topper2017-04-211-2/+10
| | | | | | | | | | to handle the targets on the second branch being commuted Currently we choose PostBB as the single successor of QFB, but its possible that QTB's single successor is QFB which would make QFB the correct choice. Differential Revision: https://reviews.llvm.org/D32323 llvm-svn: 300992
* [ConstHoisting] Add BFI in constanthoisting pass and select the best insertionWei Mi2017-04-211-30/+182
| | | | | | | | | | | | | | | | | | places based on it. Existing constant hoisting pass will merge a group of contants in a small range and hoist the const materialization code to the common dominator of their uses. However, if the uses are all in cold pathes, existing implementation may hoist the materialization code from cold pathes to a hot place. This may hurt performance. The patch introduces BFI to the pass and selects the best insertion places based on it. The change is controlled by an option consthoist-with-block-frequency which is off by default for now. Differential Revision: https://reviews.llvm.org/D28962 llvm-svn: 300989
* [AArch64][Falkor] Refine modeling of store-release exclusive instructions.Chad Rosier2017-04-212-2/+8
| | | | llvm-svn: 300987
* [Mips] Document Mips Backend Relocation PrinciplesJoel Jones2017-04-211-0/+125
| | | | | | | | | | | This revision documents the combination of C++ and table-gen code that handles relocations and addresses. Thanks for Simon Dardis for the careful reviews. Differential Revision: https://reviews.llvm.org/D31628 llvm-svn: 300986
* [AArch64][Falkor] Refine resource needs of STRQ with register offset.Chad Rosier2017-04-212-0/+8
| | | | llvm-svn: 300984
* [LV] Model if-converted phi node costsMatthew Simpson2017-04-211-2/+10
| | | | | | | | | Phi nodes in non-header blocks are converted to select instructions after if-conversion. This patch updates the cost model to account for the selects. Differential Revision: https://reviews.llvm.org/D31906 llvm-svn: 300980
* Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule ↵Daniel Sanders2017-04-214-48/+9
| | | | | | | | | predicates and support the equivalent in GIRule. It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I haven't worked out why. Reverting to make it green while I figure it out. llvm-svn: 300978
* [InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)Sanjay Patel2017-04-211-4/+14
| | | | | | | | | This matches the demanded bits behavior in the DAG and should fix: https://bugs.llvm.org/show_bug.cgi?id=32706 Differential Revision: https://reviews.llvm.org/D32255 llvm-svn: 300977
* [AArch64][Falkor] Refine loads/stores that require an extra LD pipe.Chad Rosier2017-04-212-5/+21
| | | | llvm-svn: 300976
* [AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.Chad Rosier2017-04-211-1/+1
| | | | llvm-svn: 300975
* [AArch64] Fix a few missed pre/post-inc in Falkor.Chad Rosier2017-04-211-5/+9
| | | | llvm-svn: 300974
* [ARM] GlobalISel: Add support for G_TRUNCDiana Picus2017-04-212-6/+26
| | | | | | | | Select them as copies. We only select if both the source and the destination are on the same register bank, so this shouldn't cause any trouble. llvm-svn: 300971
* [ARM] GlobalISel: Make struct arguments fail elegantlyDiana Picus2017-04-211-1/+2
| | | | | | | | | | | The condition in isSupportedType didn't handle struct/array arguments properly. Fix the check and add a test to make sure we use the fallback path in this kind of situation. The test deals with some common cases where the call lowering should error out. There are still some issues here that need to be addressed (tail calls come to mind), but they can be addressed in other patches. llvm-svn: 300967
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