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* Revert r311525: "[XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove ↵Daniel Jasper2017-08-312-63/+63
| | | | | | | | synthetic references in .text" Breaks builds internally. Will forward repo instructions to author. llvm-svn: 312243
* [SLPVectorizer] Move out Entry->NeedToGather check and assert of inner loop ↵Dinar Temirbulatov2017-08-311-5/+6
| | | | | | as invariant, NFCI. llvm-svn: 312242
* [BinaryFormat] Fix out of bounds read.Benjamin Kramer2017-08-311-1/+1
| | | | | | | Found by OSS-FUZZ! https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3220 llvm-svn: 312238
* AMD family 17h (znver1) scheduler model update.Ashutosh Nema2017-08-311-3/+1550
| | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
* [Object] Verify object sizes before handing out StringRefs pointing outBenjamin Kramer2017-08-311-12/+3
| | | | | | | | | of bounds. This can only happen on corrupt input. Found by OSS-FUZZ! https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3228 llvm-svn: 312235
* [GlobalISel][X86] Refactor X86LegalizerInfo. NFC.Igor Breger2017-08-311-45/+10
| | | | llvm-svn: 312234
* [AArch64] v8.3-a complex number supportSam Parker2017-08-315-0/+282
| | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. Differential Revision: https://reviews.llvm.org/D36792 llvm-svn: 312228
* [ARM] Reverse PostRASched subtarget feature logicSam Parker2017-08-314-24/+17
| | | | | | | | | | | | Replace the UsePostRAScheduler SubtargetFeature with DisablePostRAScheduler, which is then used by Swift and Cyclone. This patch maintains enabling PostRA scheduling for other Thumb2 capable cores and/or for functions which are being compiled in Arm mode. Differential Revision: https://reviews.llvm.org/D37055 llvm-svn: 312226
* [AArch64] IDSAR6 register assembler supportSam Parker2017-08-311-0/+3
| | | | | | | | | | The IDSAR6 system register has been introduced to identify the v8.3-a Javascript data type conversion and v8.2-a dot product support. Differential Revision: https://reviews.llvm.org/D37068 llvm-svn: 312225
* [AArch64] Support COFF linker directivesMartin Storsjo2017-08-311-0/+24
| | | | | | | | | | This is similar to what was done for ARM in SVN r269574; the code and the test are straight copypaste to the corresponding AArch64 code and test directory. Differential revision: https://reviews.llvm.org/D37204 llvm-svn: 312223
* [IRCE] Identify loops with latch comparison against current IV valueMax Kazantsev2017-08-311-11/+49
| | | | | | | | | | | | | | | Current implementation of parseLoopStructure interprets the latch comparison as a comarison against `iv.next`. If the actual comparison is made against the `iv` current value then the loop may be rejected, because this misinterpretation leads to incorrect evaluation of the latch start value. This patch teaches the IRCE to distinguish this kind of loops and perform the optimization for them. Now we use `IndVarBase` variable which can be either next or current value of the induction variable (previously we used `IndVarNext` which was always the value on next iteration). Differential Revision: https://reviews.llvm.org/D36215 llvm-svn: 312221
* Revert r312194: "[MachineOutliner] Add missed optimization remarks for the ↵Daniel Jasper2017-08-311-36/+1
| | | | | | | | | outliner." Breaks on buildbot: http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/6026/steps/test_llvm/logs/LLVM%20%3A%3A%20CodeGen__AArch64__machine-outliner-remarks.ll llvm-svn: 312219
* [IRCE][NFC] Rename IndVarNext to IndVarBaseMax Kazantsev2017-08-311-21/+21
| | | | | | | | | Renaming as a preparation step to generalizing IRCE for comparison not only against the next value of an indvar, but also against the current. Differential Revision: https://reviews.llvm.org/D36509 llvm-svn: 312215
* Temporarily revert "Update branch coalescing to be a PowerPC specific pass"Eric Christopher2017-08-317-63/+41
| | | | | | | | From comments and code review it wasn't intended to be enabled by default yet. This reverts commit r311588. llvm-svn: 312214
* AMDGPU: Don't assert in TTI with fp32 denorms enabledMatt Arsenault2017-08-311-3/+25
| | | | | | Also refine for f16 and rcp cases. llvm-svn: 312213
* Revert "llvm-mt: Fix release of OutputDoc"Vitaly Buka2017-08-311-3/+1
| | | | | | | | Multiple bots are broken. This reverts commit r312207. llvm-svn: 312212
* llvm-mt: Fix release of OutputDocVitaly Buka2017-08-311-1/+3
| | | | | | | | | | | | | | | Summary: xmlDoc needs to be released with xmlFreeDoc. Reset root element before release to avoid release of CombinedRoot owned by CombinedDoc, Reviewers: ecbeckmann, rnk, zturner, ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37321 llvm-svn: 312207
* AMDGPU: Use set for tracked registersMatt Arsenault2017-08-311-20/+23
| | | | | | | | | | | | | | | The majority of the time spent in the pass checking for the register reads. Rather than searching all of the defined registers for uses in each instruction, use a set of defined registers and check the operands of the instruction. This process still is algorithmically not great, but with the additional trick of skipping the analysis for addresses with one use, this brings one slow testcase into a reasonable range. llvm-svn: 312206
* [Orc] Add a comment about member variable dependencies to OrcMCJITReplacement.Lang Hames2017-08-311-0/+3
| | | | | | | | | The comment explains the reason behind the change in member variable order in r312086. Thanks to Philip Reames for the suggestion. llvm-svn: 312205
* Revert "Revert r312139 "Verifier: Verify the correctness of fragment ↵Adrian Prantl2017-08-311-8/+22
| | | | | | | | expressions attached to globals."" This reverts commit r312182 after fixing PR34390. llvm-svn: 312197
* Don't add a fragment expression when GlobalSRA splits up a single-member structAdrian Prantl2017-08-311-9/+12
| | | | | | | | Fixes PR34390. https://bugs.llvm.org/show_bug.cgi?id=34390 llvm-svn: 312196
* [MachineOutliner] Add missed optimization remarks for the outliner.Jessica Paquette2017-08-301-1/+36
| | | | | | | | | | | | | | This adds missed optimization remarks which report viable candidates that were not outlined because they would increase code size. Other remarks will come in separate commits. This will help to diagnose code size regressions and changes in outliner behaviour in projects using the outliner. https://reviews.llvm.org/D37085 llvm-svn: 312194
* [yaml2obj][ELF] Make symbols optional for relocationsPetr Hosek2017-08-301-1/+1
| | | | | | | | | | | | | | | | Some kinds of relocations do not have symbols, like R_X86_64_RELATIVE for instance. I would like to test this case in D36554 but currently can't because symbols are required by yaml2obj. The other option is using the empty symbol but that doesn't seem quite right to me. This change makes the Symbol field of Relocation optional and in the case where the user does not specify a symbol name the Symbol index is 0. Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D37276 llvm-svn: 312192
* [X86] Remove some code from fast isel that is no longer needed with i1 being ↵Craig Topper2017-08-301-31/+0
| | | | | | an illegal type. llvm-svn: 312190
* [SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzerMatt Morehouse2017-08-301-9/+21
| | | | | | | | | | | | | | | | | | Summary: - Don't sanitize __sancov_lowest_stack. - Don't instrument leaf functions. - Add CoverageStackDepth to Fuzzer and FuzzerNoLink. - Only enable on Linux. Reviewers: vitalybuka, kcc, george.karpenkov Reviewed By: kcc Subscribers: kubamracek, cfe-commits, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37156 llvm-svn: 312185
* Revert r312139 "Verifier: Verify the correctness of fragment expressions ↵Hans Wennborg2017-08-301-22/+8
| | | | | | | | attached to globals." This caused PR34390. llvm-svn: 312182
* [ARM] Replace fixed-size SmallSet with a bitset.Benjamin Kramer2017-08-301-30/+30
| | | | | | It's smaller. No functionality change. llvm-svn: 312180
* AMDGPU: Correct operand types for v_mad_mix*Matt Arsenault2017-08-304-13/+37
| | | | | | | | | | | | These aren't really packed instructions, so the default op_sel_hi should be 0 since this indicates a conversion. The operand types are scalar values that behave similar to an f16 scalar that may be converted to f32. Doesn't change the default printing for op_sel_hi, just the parsing. llvm-svn: 312179
* Revert r312154 "Re-enable "[MachineCopyPropagation] Extend pass to do COPY ↵Hans Wennborg2017-08-303-577/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | source forwarding"" It caused PR34387: Assertion failed: (RegNo < NumRegs && "Attempting to access record for invalid register number!") > Issues identified by buildbots addressed since original review: > - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. > - The pass no longer forwards COPYs to physical register uses, since > doing so can break code that implicitly relies on the physical > register number of the use. > - The pass no longer forwards COPYs to undef uses, since doing so > can break the machine verifier by creating LiveRanges that don't > end on a use (since the undef operand is not considered a use). > > [MachineCopyPropagation] Extend pass to do COPY source forwarding > > This change extends MachineCopyPropagation to do COPY source forwarding. > > This change also extends the MachineCopyPropagation pass to be able to > be run during register allocation, after physical registers have been > assigned, but before the virtual registers have been re-written, which > allows it to remove virtual register COPY LiveIntervals that become dead > through the forwarding of all of their uses. llvm-svn: 312178
* Simplify writeArchive return type.Rui Ueyama2017-08-303-17/+13
| | | | | | | | | | writeArchive returned a pair, but the first element of the pair is always its first argument on failure, so it doesn't make sense to return it from the function. This patch change the return type so that it does't return it. Differential Revision: https://reviews.llvm.org/D37313 llvm-svn: 312177
* SelectionDAG: Emit correct debug info for multi-register function arguments.Adrian Prantl2017-08-301-0/+21
| | | | | | | | | Previously we would just describe the first register and then call it quits. This patch emits fragment expressions for each register. <rdar://problem/34075307> llvm-svn: 312169
* [IR] Don't print "!DIExpression() = !DIExpression()" when dumpingReid Kleckner2017-08-301-1/+1
| | | | | | | | | Now that we print DIExpressions inline everywhere, we don't need to print them once as an operand and again as a value. This is only really visible when calling dump() or print() directly on a DIExpression during debugging. llvm-svn: 312168
* Refactor DIBuilder::createFragmentExpression into a static DIExpression memberAdrian Prantl2017-08-305-43/+46
| | | | | | NFC llvm-svn: 312165
* [ARM] Use Swift error registers on non-Darwin targetsBrian Gesiak2017-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Remove a check for `ARMSubtarget::isTargetDarwin` when determining whether to use Swift error registers, so that Swift errors work properly on non-Darwin ARM32 targets (specifically Android). Before this patch, generated code would save and restores ARM register r8 at the entry and returns of a function that throws. As r8 is used as a virtual return value for the object being thrown, this gets overwritten by the restore, and calling code is unable to catch the error. In turn this caused Swift code that used `do`/`try`/`catch` to work improperly on Android ARM32 targets. Addresses Swift bug report https://bugs.swift.org/browse/SR-5438. Patch by John Holdsworth. Reviewers: manmanren, rjmccall, aschwaighofer Reviewed By: aschwaighofer Subscribers: srhines, aschwaighofer, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35835 llvm-svn: 312164
* NewGVN: Make sure we add the correct user if we swapped the comparison operandsDaniel Berlin2017-08-301-2/+4
| | | | llvm-svn: 312162
* NewGVN: Allow simplification into variablesDaniel Berlin2017-08-301-22/+21
| | | | llvm-svn: 312161
* [GISel]: Add a clean up combiner during legalization.Aditya Nandakumar2017-08-301-101/+60
| | | | | | | | | | | Added a combiner which can clean up truncs/extends that are created in order to make the types work during legalization. Also moved the combineMerges to the LegalizeCombiner. https://reviews.llvm.org/D36880 llvm-svn: 312158
* [GVNSink] Remove dependency on SmallPtrSet iteration order.Benjamin Kramer2017-08-301-0/+2
| | | | | | Found by LLVM_ENABLE_REVERSE_ITERATION. llvm-svn: 312156
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-08-303-23/+577
| | | | | | | | | | | | | | | | | | | | | | | Issues identified by buildbots addressed since original review: - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 312154
* [X86] Remove unneed AVX512 check from fast isel.Craig Topper2017-08-301-2/+1
| | | | | | This is no longer necessary now that i1 is illegal. llvm-svn: 312146
* [WebAssembly] Add target feature for atomicsDerek Schuff2017-08-309-11/+31
| | | | | | | | | | Summary: This tracks the WebAssembly threads feature proposal at https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md Differential Revision: https://reviews.llvm.org/D37300 llvm-svn: 312145
* Canonicalize the representation of empty an expression in ↵Adrian Prantl2017-08-303-10/+16
| | | | | | | | | | | | | | | | DIGlobalVariableExpression This change simplifies code that has to deal with DIGlobalVariableExpression and mirrors how we treat DIExpressions in debug info intrinsics. Before this change there were two ways of representing empty expressions on globals, a nullptr and an empty !DIExpression(). If someone needs to upgrade out-of-tree testcases: perl -pi -e 's/(!DIGlobalVariableExpression\(var: ![0-9]*)\)/\1, expr: !DIExpression())/g' <MYTEST.ll> will catch 95%. llvm-svn: 312144
* [codeview] make DbgVariableLocation::extractFromMachineInstruction use OptionalBob Haarman2017-08-303-29/+31
| | | | | | | | | | | | | | | | Summary: DbgVariableLocation::extractFromMachineInstruction originally returned a boolean indicating success. This change makes it return an Optional<DbgVariableLocation> so we cannot try to access the fields of the struct if they aren't valid. Reviewers: aprantl, rnk, zturner Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37279 llvm-svn: 312143
* Verifier: Verify the correctness of fragment expressions attached to globals.Adrian Prantl2017-08-301-8/+22
| | | | llvm-svn: 312139
* [AVX512] Don't use 32-bit elements version of AND/OR/XOR/ANDN during isel ↵Craig Topper2017-08-301-32/+34
| | | | | | | | | | | | unless we're matching a masked op or broadcast Selecting 32-bit element logical ops without a select or broadcast requires matching a bitconvert on the inputs to the and. But that's a weird thing to rely on. It's entirely possible that one of the inputs doesn't have a bitcast and one does. Since there's no functional difference, just remove the extra patterns and save some isel table size. Differential Revision: https://reviews.llvm.org/D36854 llvm-svn: 312138
* [GlobalISel][X86] Support variadic function call.Igor Breger2017-08-301-4/+26
| | | | | | | | | | | | | | Summary: Support variadic function call. Port the implementation from X86FastISel. Reviewers: zvi, guyblank, oren_ben_simhon Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37261 llvm-svn: 312130
* Re-land MachineInstr: Reason locally about some memory objects before going ↵Balaram Makam2017-08-301-17/+43
| | | | | | | | | | | | | | | | | | | | to AA. Summary: Reverts r311008 to reinstate r310825 with a fix. Refine alias checking for pseudo vs value to be conservative. This fixes the original failure in builtbot unittest SingleSource/UnitTests/2003-07-09-SignedArgs. Reviewers: hfinkel, nemanjai, efriedma Reviewed By: efriedma Subscribers: bjope, mcrosier, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36900 llvm-svn: 312126
* [InstCombine] remove unnecessary vector select fold; NFCISanjay Patel2017-08-301-4/+0
| | | | | | | | | | This code is double-dead: 1. We simplify all selects with constant true/false condition in InstSimplify. I've minimized/moved the tests to show that works as expected. 2. All remaining vector selects with a constant condition are canonicalized to shufflevector, so we really can't see this pattern. llvm-svn: 312123
* fix more typos; NFCSanjay Patel2017-08-301-2/+2
| | | | llvm-svn: 312120
* fix typos; NFCSanjay Patel2017-08-301-15/+15
| | | | llvm-svn: 312119
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