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* The X86 backend has a number of optimizations for SETCC nodes which useNadav Rotem2012-08-181-6/+43
| | | | | | | | | | | | | | | | | | | | | arithmetic instructions. However, when small data types are used, a truncate node appears between the SETCC node and the arithmetic operation. This patch adds support for this pattern. Before: xorl %esi, %edi testb %dil, %dil setne %al ret After: xorb %dil, %sil setne %al ret rdar://12081007 llvm-svn: 162160
* Make atomic load and store of pointers work. Tighten verification of atomic ↵Eli Friedman2012-08-172-2/+34
| | | | | | | | | operations so other unexpected operations don't slip through. Based on patch by Logan Chien. PR11786/PR13186. llvm-svn: 162146
* Fix undefined behavior (binding a reference to a dereferenced null pointer) ifRichard Smith2012-08-171-1/+1
| | | | | | SSAUpdater was created and destroyed without being initialized. llvm-svn: 162137
* Add MipsELFWriterInfo.{h,cpp}.Akira Hatanaka2012-08-172-0/+151
| | | | llvm-svn: 162136
* Correct MCJIT functionality for MIPS32 architecture.Akira Hatanaka2012-08-178-8/+134
| | | | | | | | | | No new tests are added. All tests in ExecutionEngine/MCJIT that have been failing pass after this patch is applied (when "make check" is done on a mips board). Patch by Petar Jovanovic. llvm-svn: 162135
* Implement stack protectors for structures with character arrays in them.Bill Wendling2012-08-171-15/+40
| | | | | | <rdar://problem/10545247> llvm-svn: 162131
* Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen2012-08-171-0/+3
| | | | | | | | | PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. llvm-svn: 162130
* Add stub methods for mips assembly matcher. Akira Hatanaka2012-08-178-6/+97
| | | | | | Patch by Vladimir Medic. llvm-svn: 162124
* MemoryBuiltins: Properly guard ObjectSizeOffsetVisitor against cycles in the IR.Benjamin Kramer2012-08-171-18/+14
| | | | | | | | | | The previous fix only checked for simple cycles, use a set to catch longer cycles too. Drop the broken check from the ObjectSizeOffsetEvaluator. The BoundsChecking pass doesn't have to deal with invalid IR like InstCombine does. llvm-svn: 162120
* Change the `linker_private_weak_def_auto' linkage to `linkonce_odr_auto_hide' toBill Wendling2012-08-1711-29/+32
| | | | | | | | | | | | | | | | | | | | make it more consistent with its intended semantics. The `linker_private_weak_def_auto' linkage type was meant to automatically hide globals which never had their addresses taken. It has nothing to do with the `linker_private' linkage type, which outputs the symbols with a `l' (ell) prefix among other things. The intended semantic is more like the `linkonce_odr' linkage type. Change the name of the linkage type to `linkonce_odr_auto_hide'. And therefore changing the semantics so that it produces the correct output for the linker. Note: The old linkage name `linker_private_weak_def_auto' will still parse but is not a synonym for `linkonce_odr_auto_hide'. This should be removed in 4.0. <rdar://problem/11754934> llvm-svn: 162114
* Assert that dominates is not given a multiple edge. Finding out if we haveRafael Espindola2012-08-172-0/+17
| | | | | | | | | | | | | multiple edges between two blocks is linear. If the caller is iterating all edges leaving a BB that would be a square time algorithm. It is more efficient to have the callers handle that case. Currently the only callers are: * GVN: already avoids the multiple edge case. * Verifier: could only hit this assert when looking at an invalid invoke. Since it already rejects the invoke, just avoid computing the dominance for it. llvm-svn: 162113
* Add comment, clean up code. No functional change.Jakob Stoklund Olesen2012-08-171-30/+39
| | | | llvm-svn: 162107
* TargetLowering: Use the large shift amount during legalize types. The ↵Benjamin Kramer2012-08-171-3/+3
| | | | | | legalizer may call us with an overly large type. llvm-svn: 162101
* Use standard pattern for iterate+erase.Jakob Stoklund Olesen2012-08-171-9/+2
| | | | | | | | | Increment the MBB iterator at the top of the loop to properly handle the current (and previous) instructions getting erased. This fixes PR13625. llvm-svn: 162099
* Guard MemoryBuiltins against self-looping GEPs, which can occur in ↵Benjamin Kramer2012-08-171-0/+4
| | | | | | | | unreachable code due to constant propagation. Fixes PR13621. llvm-svn: 162098
* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-171-15/+97
| | | | llvm-svn: 162094
* Use nested switch to select arguments to reduce calls to EmitPCMP.Craig Topper2012-08-171-5/+20
| | | | llvm-svn: 162089
* Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to ↵Craig Topper2012-08-172-19/+30
| | | | | | reduce to only a single call to it thus allowing it to be inlined by the compiler. llvm-svn: 162088
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
| | | | llvm-svn: 162086
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-163-0/+51
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-165-53/+73
| | | | | | Use the target independent select analysis hooks. llvm-svn: 162060
* Add an MCID::Select flag and TII hooks for optimizing selects.Jakob Stoklund Olesen2012-08-161-16/+27
| | | | | | | | | | | | Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. llvm-svn: 162059
* Revert r162034, r162035 and r162037.Roman Divacky2012-08-162-20/+1
| | | | llvm-svn: 162039
* Define and handle additional fixup kinds. By Adhemerval Zanella.Roman Divacky2012-08-162-1/+20
| | | | llvm-svn: 162037
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
| | | | llvm-svn: 162032
* Teach GVN to reason about edges dominating uses. This allows it to handle casesRafael Espindola2012-08-162-61/+59
| | | | | | | | | | | | | where some fact lake a=b dominates a use in a phi, but doesn't dominate the basic block itself. This feature could also be implemented by splitting critical edges, but at least with the current algorithm reasoning about the dominance directly is faster. The time for running "opt -O2" in the testcase in pr10584 is 1.003 times slower and on gcc as a single file it is 1.0007 times faster. llvm-svn: 162023
* [arm-fast-isel] Add support for fastcc.Jush Lu2012-08-161-3/+6
| | | | | | | | Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. llvm-svn: 162013
* Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati2012-08-161-2/+2
| | | | llvm-svn: 162012
* (no commit message)Anitha Boyapati2012-08-161-2/+2
| | | | llvm-svn: 162010
* Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka2012-08-163-0/+18
| | | | | | floats. llvm-svn: 162008
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-155-2/+104
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Remove dead flag.Bill Wendling2012-08-151-9/+3
| | | | llvm-svn: 161990
* Fixed a problem in the JIT memory allocator whereSean Callanan2012-08-151-0/+3
| | | | | | | | | | allocations of executable memory would not be padded to account for the size of the allocation header. This resulted in undersized allocations, meaning that when the allocation was written to later the next allocation's header would be corrupted. llvm-svn: 161984
* Properly test the LLVM_USE_RVALUE_REFERENCES macro.Michael J. Spencer2012-08-152-2/+2
| | | | llvm-svn: 161978
* [PathV2] Add mapped_file_region. Implementation for Windows and POSIX.Michael J. Spencer2012-08-152-0/+311
| | | | llvm-svn: 161976
* Fix another roundToIntegral bug where very large values could become ↵Owen Anderson2012-08-151-0/+6
| | | | | | infinity. Problem and solution identified by Steve Canon. llvm-svn: 161969
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-154-2/+50
| | | | | | unaligned access. rdar://12091029 llvm-svn: 161962
* Fix typo in comment.Owen Anderson2012-08-151-1/+1
| | | | llvm-svn: 161956
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-153-28/+41
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
* Set the branch probability of branching to the 'normal' destination of an invokeBill Wendling2012-08-151-2/+30
| | | | | | | | | | instruction to something absurdly high, while setting the probability of branching to the 'unwind' destination to the bare minimum. This should set cause the normal destination's invoke blocks to be moved closer to the invoke. PR13612 llvm-svn: 161944
* [asan] implement --asan-always-slow-path, which is a part of the improvement ↵Kostya Serebryany2012-08-151-2/+5
| | | | | | to handle unaligned partially OOB accesses. See http://code.google.com/p/address-sanitizer/issues/detail?id=100 llvm-svn: 161937
* Fix a problem with APFloat::roundToIntegral where it would return incorrect ↵Owen Anderson2012-08-151-0/+12
| | | | | | results for negative inputs to trunc. Add unit tests to verify this behavior. llvm-svn: 161929
* fix infinite loop in instcombine with more than 4GB memcpyMichael Liao2012-08-151-6/+4
| | | | | | | | | | | | - memcpy size is wrongly truncated into 32-bit and treat 8GB memcpy is 0-sized memcpy - as 0-sized memcpy/memset is already removed before SimplifyMemTransfer and SimplifyMemSet in visitCallInst, replace 0 checking with assertions. - replace getZExtValue() with getLimitedValue() according to Eli Friedman llvm-svn: 161923
* Fix a typo that led to a failure to correctly verify bitcast instructions.Nick Lewycky2012-08-151-1/+1
| | | | | | Patch by Stephen Hines! llvm-svn: 161921
* Fix undefined behavior: don't perform array indexing through a potentially nullRichard Smith2012-08-151-1/+2
| | | | | | pointer. llvm-svn: 161919
* The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov2012-08-141-7/+7
| | | | | | | | reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. llvm-svn: 161907
* This needs braces. Spotted by Bill.Eric Christopher2012-08-141-1/+2
| | | | llvm-svn: 161906
* minor fix of X86ISD::VSEXT_MOVL dumpMichael Liao2012-08-141-0/+1
| | | | llvm-svn: 161902
* fix PR11334Michael Liao2012-08-144-0/+99
| | | | | | | | | | | | - FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. llvm-svn: 161894
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-142-419/+437
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
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