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* Make the global base reg GR32_NOSP.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | It can sometimes be used in addressing modes that don't support %ESP. llvm-svn: 157165
* Constrain regclasses in PeepholeOptimizer.Jakob Stoklund Olesen2012-05-201-1/+10
| | | | | | | It can be necessary to restrict to a sub-class before accessing sub-registers. llvm-svn: 157164
* Constrain register classes in TailDup.Jakob Stoklund Olesen2012-05-201-3/+5
| | | | | | | When rewriting operands, make sure the new registers have a compatible register class. llvm-svn: 157163
* When legalising shifts, do not pre-build a list of operands whichPeter Collingbourne2012-05-201-10/+14
| | | | | | | may be RAUW'd by the recursive call to LegalizeOps; instead, retrieve the other operands when calling UpdateNodeOperands. Fixes PR12889. llvm-svn: 157162
* Emit memcmp directly from the StringMatcherEmitter.Benjamin Kramer2012-05-201-4/+4
| | | | | | | | | There should be no difference in the resulting binary, given a sufficiently smart compiler. However we already had compiler timeouts on the generated code in Intrinsics.gen, this hopefully makes the lives of slow buildbots a little easier. llvm-svn: 157161
* Plug a leak when using MCJIT.Benjamin Kramer2012-05-201-1/+1
| | | | | | Found by valgrind. llvm-svn: 157160
* Add a missing PPC 64-bit stwu pattern.Hal Finkel2012-05-201-0/+8
| | | | | | | This seems to fix the remaining compile-time failures on PPC64 when compiling with -enable-ppc-preinc. llvm-svn: 157159
* Use TargetMachine's register info instead of creating a new one and leaking it.Benjamin Kramer2012-05-201-1/+1
| | | | llvm-svn: 157155
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Properly constrain register classes for sub-registers.Jakob Stoklund Olesen2012-05-201-0/+2
| | | | | | Not all GR64 registers have sub_8bit sub-registers. llvm-svn: 157150
* Properly constrain register classes in 2-addr.Jakob Stoklund Olesen2012-05-201-0/+6
| | | | | | | X86 has 2-addr instructions with different constraints on the tied def and use operands. One is GR32, one is GR32_NOSP. llvm-svn: 157149
* Missed a push_back in r157147.Jakob Stoklund Olesen2012-05-201-1/+0
| | | | llvm-svn: 157148
* Avoid deleting extra copies when RegistersDefinedFromSameValue is true.Jakob Stoklund Olesen2012-05-201-7/+8
| | | | | | | This function adds copies to be erased to DupCopies, avoid also adding them to DeadCopies. llvm-svn: 157147
* Fix build bots.Jakob Stoklund Olesen2012-05-201-4/+4
| | | | | | Avoid looking at the operands of a potentially erased instruction. llvm-svn: 157146
* LiveRangeQuery simplifies shrinkToUses().Jakob Stoklund Olesen2012-05-201-10/+6
| | | | llvm-svn: 157145
* Use LiveRangeQuery in ScheduleDAGInstrs.Jakob Stoklund Olesen2012-05-201-11/+3
| | | | llvm-svn: 157144
* Eliminate some uses of struct LiveRange.Jakob Stoklund Olesen2012-05-201-12/+15
| | | | | | That struct ought to be a LiveInterval implementation detail. llvm-svn: 157143
* Use LiveRangeQuery instead of getLiveRangeContaining().Jakob Stoklund Olesen2012-05-201-4/+4
| | | | llvm-svn: 157142
* Do not pass an invalid domtree to SimplifyInstruction fromPeter Collingbourne2012-05-201-2/+2
| | | | | | LoopUnswitch. Fixes PR12887. llvm-svn: 157140
* Simplify overlap check.Jakob Stoklund Olesen2012-05-191-8/+1
| | | | llvm-svn: 157137
* Fix 12892.Jakob Stoklund Olesen2012-05-192-4/+24
| | | | | | | | | | | | Dead code elimination during coalescing could cause a virtual register to be split into connected components. The following rewriting would be confused about the already joined copies present in the code, but without a corresponding value number in the live range. Erase all joined copies instantly when joining intervals such that the MI and LiveInterval representations are always in sync. llvm-svn: 157135
* Do not eliminate allocas whose alignment exceeds that of thePeter Collingbourne2012-05-191-12/+35
| | | | | | | copied-in constant, as a subsequent user may rely on over alignment. Fixes PR12885. llvm-svn: 157134
* Add a FIXME about access to negative stack-pointer offsets on PPC32.Hal Finkel2012-05-191-0/+2
| | | | | | | | | | | | | | The current code will generate a prologue which starts with something like: mflr 0 stw 31, -4(1) stw 0, 4(1) stwu 1, -16(1) But under the PPC32 SVR4 ABI, access to negative offsets from R1 is not allowed. This was pointed out by Peter Bergner. llvm-svn: 157133
* Remove the late DCE in RegisterCoalescer.Jakob Stoklund Olesen2012-05-191-145/+2
| | | | | | | | | | | Dead code and joined copies are now eliminated on the fly, and there is no need for a post pass. This makes the coalescer work like other modern register allocator passes: Code is changed on the fly, there is no pending list of changes to be committed. llvm-svn: 157132
* Erase joined copies immediately.Jakob Stoklund Olesen2012-05-191-8/+10
| | | | | | | | | The late dead code elimination is no longer necessary. The test changes are cause by a register hint that can be either %rdi or %rax. The choice depends on the use list order, which this patch changes. llvm-svn: 157131
* Fix an ancient bug in removeCopyByCommutingDef().Jakob Stoklund Olesen2012-05-191-2/+5
| | | | | | | | | | | | | | | Before rewriting uses of one value in A to register B, check that there are no tied uses. That would require multiple A values to be rewritten. This bug can't bite in the current version of the code for a fairly subtle reason: A tied use would have caused 2-addr to insert a copy before the use. If the copy has been coalesced, it will be found by the same loop changed by this patch, and the optimization is aborted. This was exposed by 400.perlbench and lua after applying a patch that deletes joined copies aggressively. llvm-svn: 157130
* On Haswell, perfer storing YMM registers using a single instruction.Nadav Rotem2012-05-191-5/+4
| | | | llvm-svn: 157129
* Add support for additional in-reg vbroadcast patternsNadav Rotem2012-05-191-3/+9
| | | | llvm-svn: 157127
* Collect inflatable virtual registers on the fly.Jakob Stoklund Olesen2012-05-191-16/+11
| | | | | | | There is no reason to defer the collection of virtual registers whose register class may be replaced with a larger class. llvm-svn: 157125
* Move CallbackVHs dtor inline, it can be devirtualized in many cases. Move ↵Benjamin Kramer2012-05-191-3/+6
| | | | | | the other virtual methods out of line as they are only called from within Value.cpp anyway. llvm-svn: 157123
* Tidy up some spacing and inconsistent use of pre/post increment. No ↵Craig Topper2012-05-192-28/+28
| | | | | | functional change intended. llvm-svn: 157122
* Ordinary PR1255 patch: DifferenceEngine and CPPBackend adopted to the new ↵Stepan Dyatkovskiy2012-05-191-1/+1
| | | | | | SwitchInst methods. llvm-svn: 157112
* Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748.Craig Topper2012-05-191-17/+29
| | | | llvm-svn: 157109
* Eliminate dead code after remat.Jakob Stoklund Olesen2012-05-191-1/+3
| | | | | | This will remove the original def once it has no more uses. llvm-svn: 157104
* Don't remat during updateRegDefsUses().Jakob Stoklund Olesen2012-05-191-22/+5
| | | | | | | | | | | Remaining virtreg->physreg copies were rematerialized during updateRegDefsUses(), but we already do the same thing in joinCopy() when visiting the physreg copy instruction. Eliminate the preserveSrcInt argument to reMaterializeTrivialDef(). It is now always true. llvm-svn: 157103
* Immediately erase trivially useless copies.Jakob Stoklund Olesen2012-05-191-2/+4
| | | | | | | There is no need for these instructions to stick around since they are known to be not dead. llvm-svn: 157102
* Run proper recursive dead code elimination during coalescing.Jakob Stoklund Olesen2012-05-192-21/+63
| | | | | | | | | | | | | | | Dead copies cause problems because they are trivial to coalesce, but removing them gived the live range a dangling end point. This patch enables full dead code elimination which trims live ranges to their uses so end points don't dangle. DCE may erase multiple instructions. Put the pointers in an ErasedInstrs set so we never risk visiting erased instructions in the work list. There isn't supposed to be any dead copies entering RegisterCoalescer, but they do slip by as evidenced by test/CodeGen/X86/coalescer-dce.ll. llvm-svn: 157101
* Allow LiveRangeEdit to be created with a NULL parent.Jakob Stoklund Olesen2012-05-194-9/+9
| | | | | | The dead code elimination with callbacks is still useful. llvm-svn: 157100
* Actually support DW_TAG_rvalue_reference_type that we were tryingEric Christopher2012-05-192-9/+14
| | | | | | | | to generate out of the front end. rdar://11479676 llvm-svn: 157094
* Add support for the 'd' mips inline asm output modifier.Eric Christopher2012-05-191-12/+17
| | | | | | Patch by Jack Carter. llvm-svn: 157093
* SCEV: Add MarkPendingLoopPredicates to avoid recursive isImpliedCond.Andrew Trick2012-05-191-0/+24
| | | | | | | | | | getUDivExpr attempts to simplify by checking for overflow. isLoopEntryGuardedByCond then evaluates the loop predicate which may lead to the same getUDivExpr causing endless recursion. Fixes PR12868: clang 3.2 segmentation fault. llvm-svn: 157092
* Fix replacing all the users of objc weak runtime routinesDan Gohman2012-05-181-2/+12
| | | | | | when deleting them. rdar://11434915. llvm-svn: 157080
* Modernize naming convention for class members.Jakob Stoklund Olesen2012-05-181-20/+20
| | | | | | No functional change. llvm-svn: 157079
* Move all work list processing to copyCoalesceWorkList().Jakob Stoklund Olesen2012-05-181-39/+42
| | | | | | This will make it possible to filter out erased instructions later. llvm-svn: 157073
* allow LazyValueInfo::getEdgeValue() to reason about multiple edges from the ↵Nuno Lopes2012-05-181-11/+6
| | | | | | same switch instruction by doing union of ranges (which may still be conservative, but it's more aggressive than before) llvm-svn: 157071
* Refactor data-in-code annotations.Jim Grosbach2012-05-1815-140/+212
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Remove duplicate code that we could just fallthrough to.Eric Christopher2012-05-181-1/+0
| | | | llvm-svn: 157060
* Simplify RegisterCoalescer::copyCoalesceInMBB().Jakob Stoklund Olesen2012-05-181-48/+15
| | | | | | | | | It is no longer necessary to separate VirtCopies, PhysCopies, and ImpDefCopies. Implicitly defined copies are extremely rare after we added the ProcessImplicitDefs pass, and physical register copies are not joined any longer. llvm-svn: 157059
* Add support for the mips 'x' inline asm modifier.Eric Christopher2012-05-181-0/+5
| | | | | | Patch by Jack Carter. llvm-svn: 157057
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