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* Add and Operator== method to ValID so equality can be done properly forReid Spencer2007-03-191-0/+20
| | | | | | named or numbered ValIDs. llvm-svn: 35172
* For PR1258:Reid Spencer2007-03-191-39/+20
| | | | | | | | | | Radically simplify the SlotMachine. There is no need to keep Value planes around any more. This change causes slot numbering to number all un-named, non-void values starting at 0 and incrementing monotonically through the function, regardless of type (including BasicBlocks). Getting slot numbers is now a single lookup operation instead of a double lookup. llvm-svn: 35171
* fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.llChris Lattner2007-03-191-1/+2
| | | | llvm-svn: 35169
* Remove -reduce-joining-phys-regs options. Make it on by default.Evan Cheng2007-03-191-3/+1
| | | | llvm-svn: 35165
* Fix naming inconsistencies.Evan Cheng2007-03-196-30/+30
| | | | llvm-svn: 35163
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-193-2/+12
| | | | | | rematerializable. Only used for constant generation for now. llvm-svn: 35162
* Constant generation instructions are re-materializable.Evan Cheng2007-03-192-5/+11
| | | | llvm-svn: 35161
* Added isReMaterializable.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35160
* Minor bug fix.Evan Cheng2007-03-191-1/+1
| | | | llvm-svn: 35153
* fix a warningChris Lattner2007-03-191-1/+1
| | | | llvm-svn: 35152
* implement the next chunk of SROA with memset/memcpy's of aggregates. ThisChris Lattner2007-03-191-36/+107
| | | | | | implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll llvm-svn: 35150
* Clean up this code and fix subtract miscompile.Nick Lewycky2007-03-181-18/+22
| | | | llvm-svn: 35146
* Implement InstCombine/and-xor-merge.ll:test[12].Chris Lattner2007-03-181-54/+96
| | | | | | Rearrange some code to simplify it now that shifts are binops llvm-svn: 35145
* minor updatesChris Lattner2007-03-181-8/+6
| | | | llvm-svn: 35143
* This is implemented. We now generate:Nick Lewycky2007-03-181-40/+0
| | | | | | | | | | | | | | | | | | | | | | entry: icmp ugt i32 %x, 4 ; <i1>:0 [#uses=1] br i1 %0, label %cond_true, label %cond_false cond_true: ; preds = %entry %tmp1 = tail call i32 (...)* @bar( i32 12 ) ; <i32> [#uses=0] ret void cond_false: ; preds = %entry switch i32 %x, label %cond_true15 [ i32 4, label %cond_true3 i32 3, label %cond_true7 i32 2, label %cond_true11 i32 0, label %cond_false17 ] ... llvm-svn: 35142
* - Merge UsedBlocks info after two virtual registers are coalesced.Evan Cheng2007-03-181-23/+30
| | | | | | - Use distance to closest use to determine whether to abort coalescing. llvm-svn: 35141
* Keep UsedBlocks info accurate.Evan Cheng2007-03-182-0/+6
| | | | llvm-svn: 35140
* Propagate ValueRanges across equality.Nick Lewycky2007-03-181-67/+159
| | | | | | Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0. llvm-svn: 35138
* Silence warningAnton Korobeynikov2007-03-171-2/+2
| | | | llvm-svn: 35137
* Track the BB's where each virtual register is used.Evan Cheng2007-03-171-15/+22
| | | | llvm-svn: 35135
* Joining a live interval of a physical register with a virtual one can turn outEvan Cheng2007-03-171-0/+54
| | | | | | | | | | | | to be really bad. Once they are joined they are not broken apart. Also, physical intervals cannot be spilled! Added a heuristic as a workaround for this. Be careful coalescing with a physical register if the virtual register uses are "far". Check if there are uses in the same loop as the source (copy instruction). Check if it is in the loop preheader, etc. llvm-svn: 35134
* Use SmallSet instead of std::set.Evan Cheng2007-03-171-1/+1
| | | | llvm-svn: 35133
* If sdisel has decided to sink GEP index expression into any BB. Replace all usesEvan Cheng2007-03-171-22/+37
| | | | | | in that BB. llvm-svn: 35132
* Support 'I' inline asm constraint.Devang Patel2007-03-171-0/+11
| | | | llvm-svn: 35129
* Only ARMv6 has BSWAP.Lauro Ramos Venancio2007-03-161-0/+4
| | | | | | Fix MultiSource/Applications/aha test. llvm-svn: 35128
* Turn on GEP index sinking by default.Evan Cheng2007-03-161-7/+0
| | | | llvm-svn: 35127
* Stupid bug.Evan Cheng2007-03-161-1/+1
| | | | llvm-svn: 35126
* And now support for MMX logical operations.Bill Wendling2007-03-162-2/+54
| | | | llvm-svn: 35125
* Sink a binary expression into its use blocks if it is a loop invariantEvan Cheng2007-03-161-0/+92
| | | | | | | computation used as GEP indexes and if the expression can be folded into target addressing mode of GEP load / store use types. llvm-svn: 35123
* Added isLegalAddressExpression(). Only allows X +/- C for now.Evan Cheng2007-03-162-0/+21
| | | | llvm-svn: 35122
* Added isLegalAddressExpression hook to test if the given expression can beEvan Cheng2007-03-161-0/+8
| | | | | | folded into target addressing mode for the given type. llvm-svn: 35121
* Add more comments and update to new asm syntax.Nick Lewycky2007-03-161-28/+130
| | | | | | | | | | Add new micro-optimizations. Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes "icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing support for NE values in ValueRanges. llvm-svn: 35119
* Multiplication support for MMX.Bill Wendling2007-03-152-1/+9
| | | | llvm-svn: 35118
* Debugging output stuff.Evan Cheng2007-03-151-4/+4
| | | | llvm-svn: 35117
* Estimate a cost using the possible number of scratch registers required and useEvan Cheng2007-03-141-9/+47
| | | | | | | | | | it as a late BURR scheduling tie-breaker. Intuitively, it's good to push down instructions whose results are liveout so their long live ranges won't conflict with other values which are needed inside the BB. Further prioritize liveout instructions by the number of operands which are calculated within the BB. llvm-svn: 35109
* Under X86-64 large code model, do not emit 32-bit pc relative calls.Evan Cheng2007-03-141-3/+5
| | | | llvm-svn: 35108
* Notes about codegen issues.Evan Cheng2007-03-141-0/+47
| | | | llvm-svn: 35107
* Clean up.Evan Cheng2007-03-141-3/+4
| | | | llvm-svn: 35105
* Oops.Evan Cheng2007-03-141-1/+1
| | | | llvm-svn: 35104
* X86-64 JIT is in large code model. Need stubs for direct calls.Evan Cheng2007-03-141-1/+1
| | | | llvm-svn: 35097
* x86-64 JIT stub codegen.Evan Cheng2007-03-141-0/+11
| | | | llvm-svn: 35096
* Preliminary support for X86-64 JIT stub codegen.Evan Cheng2007-03-141-3/+35
| | | | llvm-svn: 35095
* ShiftAmt might equal to zero. Handle this situation.Zhou Sheng2007-03-141-7/+9
| | | | llvm-svn: 35094
* Enable KnownZero/One.clear().Zhou Sheng2007-03-141-2/+2
| | | | llvm-svn: 35093
* Try schedule def + use closer whne Sethi-Ullman numbers are the same.Evan Cheng2007-03-131-6/+38
| | | | | | | | | | | | | | | | | | | | | e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. llvm-svn: 35089
* AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]Evan Cheng2007-03-131-0/+23
| | | | llvm-svn: 35088
* Zero is always a legal AM immediate.Evan Cheng2007-03-131-0/+3
| | | | llvm-svn: 35087
* Correct type info for isLegalAddressImmediate() check.Evan Cheng2007-03-131-12/+18
| | | | llvm-svn: 35086
* Stack and register alignment of call arguments in the ELF ABINicolas Geoffray2007-03-131-6/+52
| | | | llvm-svn: 35083
* ifdef out some dead code.Chris Lattner2007-03-131-2/+8
| | | | | | Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll llvm-svn: 35082
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