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* [libFuzzer] enable use_cmp by defaultKostya Serebryany2016-10-2711-15/+17
| | | | llvm-svn: 285353
* [APFloat] Add DoubleAPFloat mode to APFloat. NFC.Tim Shen2016-10-271-59/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds DoubleAPFloat mode to APFloat. Now, an APFloat with semantics PPCDoubleDouble will have DoubleAPFloat layout (APFloat.U.Double), which contains two underlying APFloats as PPCDoubleDoubleImpl and IEEEdouble semantics. Currently the IEEEdouble APFloat is not used, and the first APFloat behaves exactly the same before this change. This patch consists of three kinds of logics: 1) Construction and destruction of APFloat. Now the ctors, dtor, assign opertors and factory functions construct different underlying layout based on the semantics passed in. 2) s/IEEE/getIEEE()/ for normal, lifetime-unrelated computation functions. These functions only access Floats[0] in DoubleAPFloat, which is the same as today's semantic. 3) A "Double dispatch" function, APFloat::convert. Converting between two different layouts requires appropriate logic. Neither of these change the external behavior. Reviewers: hfinkel, kbarton, echristo, iteratee Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D25977 llvm-svn: 285351
* BitcodeReader: Require clients to read the block info block at most once.Peter Collingbourne2016-10-271-2/+2
| | | | | | | | | | | | This change makes it the client's responsibility to call ReadBlockInfoBlock() at most once. This is in preparation for a future change that will allow there to be multiple block info blocks. See also: http://lists.llvm.org/pipermail/llvm-dev/2016-October/106512.html Differential Revision: https://reviews.llvm.org/D26016 llvm-svn: 285350
* CodeGen: Handle missed case of block removal during BlockPlacement.Kyle Butt2016-10-271-4/+10
| | | | | | | | | There is a use after free bug in the existing code. Loop layout selects a preferred exit block, and then lays out the loop. If this block is removed during layout, it needs to be invalidated to prevent a use after free. llvm-svn: 285348
* [InstCombine] fix foldSPFofSPF() to handle vector splatsSanjay Patel2016-10-271-22/+18
| | | | llvm-svn: 285345
* Another additional error check for invalid Mach-O files for theKevin Enderby2016-10-271-0/+26
| | | | | | | | | | | | | | | | | | | | | | obsolete load commands. Again the philosophy of the error checking in libObject for Mach-O files, the idea behind the checking is that we never will return a Mach-O file out of libObject that contains unknown things the library code can’t operate on. So known obsolete load commands will cause a hard error. Also to make things clear I have added comments to the values and structures in Support/Mach-O.h and Support/MachO.def as to what is obsolete. As noted in a TODO in the code, there may need to be a non-default mode to allow some unknown values for well structured Mach-O files with things like unknown load load commands. So things like using an old lldb on a newer Mach-O file could still provide some limited functionality. llvm-svn: 285342
* AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizerTom Stellard2016-10-272-0/+20
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25528 llvm-svn: 285338
* [LoopUnroll] Check partial unrolling is enabled before initialization. NFC.Haicheng Wu2016-10-271-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D23891 llvm-svn: 285330
* [X86][AVX512] Fix MUL v8i64 costs on non-AVX512DQ targetsSimon Pilgrim2016-10-271-0/+1
| | | | llvm-svn: 285329
* [InstCombine] handle simple vector integer constants in IsFreeToInvertSanjay Patel2016-10-271-0/+18
| | | | llvm-svn: 285318
* [X86][AVX512DQ] Move v2i64 and v4i64 MUL lowering to tablegenSimon Pilgrim2016-10-272-23/+21
| | | | | | As suggested by @igorb on D26011 llvm-svn: 285313
* ARM: ensure that the Windows DBZ check is in rangeSaleem Abdulrasool2016-10-272-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Windows ARM target expects the compiler to emit a division-by-zero check. The check would use the form of: cmp r?, #0 cbz .Ltrap b .Lbody .Lbody: ... .Ltrap: udf #249 @ __brkdiv0 This works great most of the time. However, if the body of the function is greater than 127 bytes, the branch target limitation of cbz becomes an issue. This occurs in the unoptimized code generation cases sometimes (like in compiler-rt). Since this is a matter of correctness, possibly pay a small penalty instead. We now form this slightly differently: cbnz .Lbody udf #249 @ __brkdiv0 .Lbody: ... The positive case is through the branch instead of being the next instruction. However, because of the basic block layout, the negated branch is going to be a short distance always (2 bytes away, after the inserted __brkdiv0). The new t__brkdiv0 instruction is required to explicitly mark the instruction as a terminator as the generic UDF instruction is not a terminator. Addresses PR30532! llvm-svn: 285312
* Switch all DWARF variables for tags, attributes and forms over to use the ↵Greg Clayton2016-10-274-37/+47
| | | | | | | | llvm::dwarf enumerations instead of using raw uint16_t values. This allows easier debugging as users can see the values of the enumerations in the variables view that will show the enumeration string instead of just a number. https://reviews.llvm.org/D26013 llvm-svn: 285309
* Add Loop Sink pass to reverse the LICM based of basic block frequency.Dehao Chen2016-10-274-14/+337
| | | | | | | | | | | | Summary: LICM may hoist instructions to preheader speculatively. Before code generation, we need to sink down the hoisted instructions inside to loop if it's beneficial. This pass is a reverse of LICM: looking at instructions in preheader and sinks the instruction to basic blocks inside the loop body if basic block frequency is smaller than the preheader frequency. Reviewers: hfinkel, davidxl, chandlerc Subscribers: anna, modocache, mgorny, beanz, reames, dberlin, chandlerc, mcrosier, junbuml, sanjoy, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D22778 llvm-svn: 285308
* [mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass.Vasileios Kalintiris2016-10-271-3/+0
| | | | | | | | | | | | | | r282428 added the MipsOptimizePICCall as an opt-in pass that can be skipped when using the -opt-bisect-limit option. However, this pass is needed because it generates code that conforms to the o32 ABI specification by using the $t9 register for PIC calls with JALR instructions. This bug was exposed by the fact that skipFunction() also checks for the "optnone" attribute. This caused functions with that attribute to break the requirements of the o32 ABI. llvm-svn: 285305
* [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64Simon Pilgrim2016-10-272-0/+32
| | | | | | | | | | With DQI but without VLX, lower v2i64 and v4i64 MUL operations with v8i64 MUL (vpmullq). Updated cost table accordingly. Differential Revision: https://reviews.llvm.org/D26011 llvm-svn: 285304
* [ValueTracking] fix matchSelectPattern to allow vector splat folds of ↵Sanjay Patel2016-10-271-6/+8
| | | | | | min/max/abs/nabs llvm-svn: 285303
* Fix memory issue in AttrBuilder::removeAttribute uses.Bjorn Pettersson2016-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Found when running Valgrind. This removes two unnecessary assignments when using AttrBuilder::removeAttribute. AttrBuilder::removeAttribute returns a reference to the object. As the LHSes were the same as the callees, the assignments resulted in memcpy calls where dst = src. Commited on behalf-of: dstenb (David Stenberg) Reviewers: mkuper, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25460 llvm-svn: 285298
* [Hexagon] Do not expand ISD::SELECT for HVX vectorsKrzysztof Parzyszek2016-10-272-16/+19
| | | | llvm-svn: 285297
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsSimon Pilgrim2016-10-271-13/+111
| | | | | | | | | | | | | | | | Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285296
* [SLP] Fix for PR30626: Compiler crash inside SLP Vectorizer.Alexey Bataev2016-10-271-4/+11
| | | | | | | | | | | | | | | | After successfull horizontal reduction vectorization attempt for PHI node vectorizer tries to update root binary op by combining vectorized tree and the ReductionPHI node. But during vectorization this ReductionPHI can be vectorized itself and replaced by the `undef` value, while the instruction itself is marked for deletion. This 'marked for deletion' PHI node then can be used in new binary operation, causing "Use still stuck around after Def is destroyed" crash upon PHI node deletion. Also the test is fixed to make it perform actual testing. Differential Revision: https://reviews.llvm.org/D25671 llvm-svn: 285286
* [ARM] Predicate UMAAL selection on hasDSP.Sam Parker2016-10-272-2/+3
| | | | | | | | | | | | UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets. Also fix wrong CHECK prefix in longMAC.ll test. Patch by Vadzim Dambrouski. Differential Revision: https://reviews.llvm.org/D25890 llvm-svn: 285278
* [AVR] Generate all of the TableGen files we needDylan McKay2016-10-271-1/+6
| | | | | | | This enables generation of all of the TableGen files that are used downstream. llvm-svn: 285274
* AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged due register ↵Nicolai Haehnle2016-10-271-11/+31
| | | | | | | | | | | | | | | | | | | | | | | | dependencies Summary: When finding a match for a merge and collecting the instructions that must be moved, keep in mind that the instruction we merge might actually use one of the defs that are being moved. Fixes piglit spec/arb_enhanced_layouts/execution/component-layout/vs-tcs-load-output[-indirect]. The fact that the ds_read in the test case is not eliminated suggests that there might be another problem related to alias analysis, but that's a separate problem: this pass should still work correctly even when earlier optimization passes missed something or were disabled. Reviewers: tstellarAMD, arsenm Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25829 llvm-svn: 285273
* [AVR] Compile the disassemblerDylan McKay2016-10-273-6/+3
| | | | | | | This also updates references of 'TheAVRTarget' to the new 'getTheAVRTarget()' method. llvm-svn: 285272
* [AVR] Add AVRISelDAGToDAG.cppDylan McKay2016-10-272-0/+564
| | | | | | | | | | | | Summary: This pulls the AVR instruction selector in-tree. Reviewers: arsenm, kparzysz Subscribers: llvm-commits, wdng, beanz, japaric, mgorny Differential Revision: https://reviews.llvm.org/D25278 llvm-svn: 285270
* [AVR] Add the machine code emitterDylan McKay2016-10-274-0/+423
| | | | | | | | | | Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, japaric, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D25388 llvm-svn: 285269
* [PowerPC] - No SExt/ZExt needed for count trailing zerosNemanja Ivanovic2016-10-271-2/+4
| | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D25896 It just eliminates the redundant ZExt after a count trailing zeros instruction. llvm-svn: 285267
* [libFuzzer] speculatively trying to fix the Mac build; second attemptKostya Serebryany2016-10-272-14/+4
| | | | llvm-svn: 285262
* [libFuzzer] revert 285259 -- hit commit too soonKostya Serebryany2016-10-271-4/+1
| | | | llvm-svn: 285260
* [libFuzzer] speculatively trying to fix the Mac buildKostya Serebryany2016-10-271-1/+4
| | | | llvm-svn: 285259
* [AArch64] Create feature set for Samsung Exynos-M2Evandro Menezes2016-10-261-13/+24
| | | | | | | | Since Exynos-M2 improved the FP square root unit a bit over the one in Exynos-M1, it does not benefit from using the Newton series for such operations. llvm-svn: 285246
* DebugInfo: fix incorrect alignment type (NFC)Victor Leschuk2016-10-264-11/+22
| | | | | | | | | Change type of some missed DebugInfo-related alignment variables, that are still uint64_t, to uint32_t. Original change introduced in r284482. llvm-svn: 285242
* ARM: don't rely on push/pop reglists being in order when folding SP adjust.Tim Northover2016-10-261-8/+19
| | | | | | | | | | | | | | | | | | It would be a very nice invariant to rely on, but unfortunately it doesn't necessarily hold (and the causes of mis-sorted reglists appear to be quite varied) so to be robust the frame lowering code can't assume that the first register in the list is also the first one that actually gets pushed. Should fix an issue where we were turning something like: push {r8, r4, r7, lr} sub sp, #24 into nonsense like: push {r2, r3, r4, r5, r6, r7, r8, r4, r7, lr} llvm-svn: 285232
* Do not assume that FP vector operands are never legalized by expandingNemanja Ivanovic2016-10-261-1/+2
| | | | | | | | | | | This patch ensures that if a floating point vector operand is legalized by expanding, it is legalized through the stack rather than by calling DAGTypeLegalizer::IntegerToVector which will cause a failure since the operand is a non-integer type. This fixes PR 30715. llvm-svn: 285231
* Simplify `x >=u x >> y` and `x >=u x udiv y`Sanjoy Das2016-10-261-0/+11
| | | | | | | | | | | | | | | | | | | Summary: Extends InstSimplify to handle both `x >=u x >> y` and `x >=u x udiv y`. This is a folloup of rL258422 and https://github.com/rust-lang/rust/pull/30917 where llvm failed to optimize away the bounds checking in a binary search. Patch by Arthur Silva! Reviewers: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25941 llvm-svn: 285228
* Revert "[AliasSetTracker] Make AST smarter about intrinsics that don't ↵Chad Rosier2016-10-261-15/+0
| | | | | | | | | | | actually affect memory." This reverts commit r285191. LICM appears to rely on the Alias Set Tracker hitting lifetime markers to prevent code from being moved outside of the original scope. llvm-svn: 285227
* [PowerPC] Implement vec_insert_exp builtins - llvm portionNemanja Ivanovic2016-10-261-2/+2
| | | | | | | This revision corresponds to review: https://reviews.llvm.org/D25957. Committing on behalf of Zaara Syeda. llvm-svn: 285225
* [libFuzzer] simplify TracePC::HandleTrace even further. Also, when dealing ↵Kostya Serebryany2016-10-263-29/+5
| | | | | | with -exit_on_src_pos, symbolize every PC only once llvm-svn: 285223
* [AArch64] Avoid materializing constant 1 when generating cneg instructions.Chad Rosier2016-10-261-2/+13
| | | | | | | | | | | | | | | | | Instead of cmp w0, #1 orr w8, wzr, #0x1 cneg w0, w8, ne we now generate cmp w0, #1 csinv w0, w0, wzr, eq PR28965 llvm-svn: 285217
* [WebAssembly] Update the README.txt.Dan Gohman2016-10-261-9/+17
| | | | | | | | Update the README.txt with newer information, add a link to the Emscripten page explaining the current easiest way to use the LLVM wasm backend, and mention that other ways of using the LLVM wasm backend are in development. llvm-svn: 285215
* [MC] Fix comma typo in .loc parsingNirav Dave2016-10-261-1/+1
| | | | llvm-svn: 285214
* Reapply: "Remove debug location from common tail when tail-merging"Robert Lougher2016-10-261-2/+5
| | | | | | | | | | | | | | | | This reapplies revision 285093. Original commit message: The branch folding pass tail merges blocks into a common-tail. However, the tail retains the debug information from one of the original inputs to the merge (chosen randomly). This is a problem for sampled-based PGO, as hits on the common-tail will be attributed to whichever block was chosen, irrespective of which path was actually taken to the common-tail. This patch fixes the issue by nulling the debug location for the common-tail. Differential Revision: https://reviews.llvm.org/D25742 llvm-svn: 285212
* AMDGPU: Refactor processor definition to use ISA version featuresYaxun Liu2016-10-264-34/+118
| | | | | | | | | | | | | | Add missing ISA versions 7.0.2/8.0.4/8.1.0. to backend. Refactor processor definition to use ISA version features. Fixed ISA version for stoney. Based on Laurent Morichetti's patch. Differential Revision: https://reviews.llvm.org/D25919 llvm-svn: 285210
* Introduce updateDiscriminator interface to DILocation to make it cleaner ↵Dehao Chen2016-10-261-30/+7
| | | | | | | | | | | | | | assigning discriminators. Summary: This patch introduces updateDiscriminator to DILocation so that it can be directly called by AddDiscriminator. It also makes it easier to update the discriminator later. Reviewers: dnovillo, dblaikie, aprantl, echristo Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D25959 llvm-svn: 285207
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-262-14/+100
| | | | | | This reverts r283003 llvm-svn: 285203
* AMDGPU: Fix counting si_mask_branch as 4 bytesMatt Arsenault2016-10-262-1/+1
| | | | llvm-svn: 285202
* Fix nondeterministic output in local stack slot alloc passMatt Arsenault2016-10-261-6/+16
| | | | | | | | | | This finds all of the references to a frame index in a function, and sorts by the offset. If multiple instructions use the same offset, nothing was breaking the tie for sorting. This avoids the test failures the reverted r282999 introduced. llvm-svn: 285201
* [InstCombine] clean up commonCastTransforms; NFCSanjay Patel2016-10-261-11/+9
| | | | | | | | 1. Use 'auto' with dyn_cast. 2. Variables start with a capital letter. 3. Use proper punctuation in comments. llvm-svn: 285200
* LegalizeDAG: Support promoting [US]DIV and [US]REM operationsTom Stellard2016-10-261-1/+18
| | | | | | | | | | | | | | | | | | Summary: AMDGPU will need this one i16 is added as a legal type. This is tested by: test/CodeGen/AMDGPU/sdiv.ll test/CodeGen/AMDGPU/sdivrem24.ll test/CodeGen/AMDGPU/udiv.ll test/CodeGen/AMDGPU/udivrem24.ll Reviewers: bogner, efriedma Subscribers: efriedma, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D25699 llvm-svn: 285199
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