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* Fix some comment typos.Benjamin Kramer2015-08-0853-157/+159
| | | | llvm-svn: 244402
* [X86] Add ADX and RDSEED to Skylake processor.Craig Topper2015-08-081-1/+2
| | | | llvm-svn: 244396
* Add SlowBTMem to Sandy Bridge and newer Intel CPUs. Reading through Agner ↵Craig Topper2015-08-081-5/+9
| | | | | | Fog's table suggests there have been no improvements to these processors relative to Westmere for bit test instructions. llvm-svn: 244395
* [InstCombine] Don't try to sink EH pad instructionsDavid Majnemer2015-08-081-2/+2
| | | | | | | Found by inspection, this change should not effect the existing landingpad behavior. llvm-svn: 244391
* Add model numbers for Skylake CPUs and an additional Broadwell model.Craig Topper2015-08-081-0/+6
| | | | llvm-svn: 244385
* Add Intel family 6 model 93 as Silvermont.Craig Topper2015-08-081-0/+1
| | | | llvm-svn: 244384
* AMDGPU/SI: Another attempt to fix Windows bots broken by r244372Tom Stellard2015-08-081-1/+1
| | | | llvm-svn: 244383
* Remove unnecessary includesMatt Arsenault2015-08-082-2/+0
| | | | llvm-svn: 244382
* AMDGPU: Implement AMDGPUOperand::print()Matt Arsenault2015-08-081-1/+16
| | | | llvm-svn: 244381
* AMDGPU/SI: Remove VCCRegMatt Arsenault2015-08-086-31/+48
| | | | llvm-svn: 244380
* AMDGPU/SI: Remove source uses of VCCRegMatt Arsenault2015-08-084-15/+38
| | | | llvm-svn: 244379
* AMDGPU/SI: Attempt to fix Windows bots broken by r244372Tom Stellard2015-08-081-1/+1
| | | | llvm-svn: 244376
* Convert getSymbolSection to return an ErrorOr.Rafael Espindola2015-08-078-40/+34
| | | | | | | This function can actually fail since the symbol contains an index to the section and that can be invalid. llvm-svn: 244375
* AMDGPU: Add pass to lower OpenCL image and sampler arguments.Tom Stellard2015-08-074-0/+373
| | | | | | | | | The pass adds new kernel arguments for image attributes, and resolves calls to dummy attribute and resource id getter functions. Patch by: Zoltan Gilian llvm-svn: 244372
* [LAA] Remove unused pointer partition argument from getNumberOfChecks, NFCAdam Nemet2015-08-071-14/+1
| | | | | | | | | This is unused after filtering checks was moved to the clients. As a result, we can just return the number of the checks in the precomputed set. llvm-svn: 244369
* [LAA] Make the set of runtime checks part of the state of LAA, NFCAdam Nemet2015-08-072-4/+11
| | | | | | | | | | | | | | | | | | | | This is the full set of checks that clients can further filter. IOW, it's client-agnostic. This makes LAA complete in the sense that it now provides the two main results of its analysis precomputed: 1. memory dependences via getDepChecker().getInsterestingDependences() 2. run-time checks via getRuntimePointerCheck().getChecks() However, as a consequence we now compute this information pro-actively. Thus if the client decides to skip the loop based on the dependences we've computed the checks unnecessarily. In order to see whether this was a significant overhead I checked compile time on SPEC2k6 LTO bitcode files. The change was in the noise. The checks are generated in canCheckPtrAtRT, at the same place where we used to call groupChecks to merge checks. llvm-svn: 244368
* [AArch64][LoadStoreOptimizer] Turn a test into an assert. NFC.Quentin Colombet2015-08-071-2/+2
| | | | | | | | | At this point the given Opc must be valid, otherwise we should not look for a matching pair to form paired load or store. Thanks to Chad to point out this piece of code! llvm-svn: 244366
* AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructionsTom Stellard2015-08-072-14/+38
| | | | | | | | | | | | | | | | Summary: With InstAlias, we don't need to print the _e32 portion of the mnemonic when we print the $dst operand. This change makes it possible to include vcc in the asm string when we switch VOPC over to having implicit vcc defs. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11813 llvm-svn: 244362
* MIR Serialization: Serialize the base alignment for the machine memory operands.Alex Lorenz2015-08-074-4/+18
| | | | llvm-svn: 244357
* MIR Serialization: Serialize the offsets for the machine memory operands.Alex Lorenz2015-08-072-1/+6
| | | | llvm-svn: 244356
* MIR Parser: Extract the parsing of the operand's offset into a new method. NFC.Alex Lorenz2015-08-071-2/+10
| | | | | | | | This commit extract the code that parses the 64-bit offset from the method 'parseOperandsOffset' to a new method 'parseOffset' so that we can reuse it when parsing the offset for the machine memory operands. llvm-svn: 244355
* AMDGPU: Assume SMRD access for constant address spaceMatt Arsenault2015-08-072-40/+76
| | | | | | | Since r243294 these are selected to SMRD and moved later if required. llvm-svn: 244354
* Add Intel family 6 model 90 as Silvermont. Fixes PR24392.Craig Topper2015-08-071-0/+1
| | | | llvm-svn: 244352
* [LAA] Remove unused pointer partition argument from print(), NFCAdam Nemet2015-08-071-4/+2
| | | | | | | This is now handled in the client. No need for LAA to provide this variant. llvm-svn: 244349
* [ConstantFoldTerminator] Preserve make.implicit metadata when converting ↵Chen Li2015-08-071-0/+5
| | | | | | | | | | | | | | SwitchInst to BranchInst Summary: llvm::ConstantFoldTerminator function can convert SwitchInst with single case (and default) to a conditional BranchInst. This patch adds support to preserve make.implicit metadata on this conversion. Reviewers: sanjoy, weimingz, chenli Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D11841 llvm-svn: 244348
* [InstCombine] Fix SSE2/AVX2 vector logical shift by constantSimon Pilgrim2015-08-071-16/+39
| | | | | | | | | | | | | | | | This patch fixes the sse2/avx2 vector shift by constant instcombine call to correctly deal with the fact that the shift amount is formed from the entire lower 64-bit and not just the lowest element as it currently assumes. e.g. %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>) In this case, (V)PSRLD doesn't perform a lshr by 15 but in fact attempts to shift by 64424509455 ((15 << 32) | 15) - giving a zero result. In addition, this review also recognizes shift-by-zero from a ConstantAggregateZero type (PR23821). Differential Revision: http://reviews.llvm.org/D11760 llvm-svn: 244341
* Add functions to save and restore the PrettyStackTrace state.Nico Weber2015-08-071-0/+14
| | | | | | | | | | | | | | | | PrettyStackTraceHead is a LLVM_THREAD_LOCAL, which means it's just a global in LLVM_ENABLE_THREADS=NO builds. If a CrashRecoveryContext is used with code that uses PrettyStackEntries, and a crash happens, PrettyStackTraceHead is currently not reset to its pre-crash value. These functions make it possible to add a cleanup to such code that does this. (Not reseting the value then causes the assert in ~PrettyStackTraceEntry() to fire if the code outside of the CrashRecoveryContext also uses PrettyStackEntries -- for example, clang when building a module.) Part of PR11974. llvm-svn: 244338
* Add a comment.Nico Weber2015-08-071-0/+4
| | | | llvm-svn: 244337
* [ARM] Remove an unused reference to MachineRegisterInfo. NFC.Chad Rosier2015-08-071-2/+1
| | | | llvm-svn: 244334
* AMDGPU/SI: Use correct encoding of vopc for VI in the assemblerTom Stellard2015-08-071-0/+2
| | | | | | | | | | | | Summary: We were using the SI encoding for VI. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11812 llvm-svn: 244332
* AMDGPU/SI: v_mac_legacy_f32 does not exist on VITom Stellard2015-08-071-6/+6
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11810 llvm-svn: 244322
* AMDGPU/SI: Remove unused outs parameter from VOPC TableGen classesTom Stellard2015-08-071-5/+5
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11809 llvm-svn: 244321
* Add dynamic_table iterators back to ELF.h.Rafael Espindola2015-08-071-0/+2
| | | | | | | | | In tree they are only used by llvm-readobj, but it is also used by https://github.com/mono/CppSharp. While at it, add some missing error checking. llvm-svn: 244320
* [MC/Dwarf] Allow to specify custom parameters for linetable emission.Frederic Riss2015-08-074-53/+56
| | | | | | | | | NFC patch for current users, but llvm-dsymutil will use the new functionality to adapt to the input linetable. Based on a patch by Adrian Prantl. llvm-svn: 244318
* Fix unused variable warning introduced in r244314Silviu Baranga2015-08-071-2/+4
| | | | llvm-svn: 244315
* [ARM] Update ReconstructShuffle to handle mismatched typesSilviu Baranga2015-08-071-92/+154
| | | | | | | | | | | | | | | | | | Summary: Port the ReconstructShuffle function from AArch64 to ARM to handle mismatched incoming types in the BUILD_VECTOR node. This fixes an outstanding FIXME in the ReconstructShuffle code. Reviewers: t.p.northover, rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11720 llvm-svn: 244314
* Revert "Make global aliases have symbol size equal to their type"John Brawn2015-08-071-10/+0
| | | | | | | This reverts r242520, as it caused pr24379. Also removes part of the test added by r243874 that checks the size of alias symbols. llvm-svn: 244313
* ShrinkWrap.cpp: Tweak r244235 for a non-functional member, PredicateFtor. ↵NAKAMURA Takumi2015-08-071-2/+2
| | | | | | [-Wdocumentation] llvm-svn: 244309
* WebAssembly: textual emission uses expected opcode namesJF Bastien2015-08-071-12/+13
| | | | | | | | | | | | Summary: WebAssembly's tablegen instructions have the names WebAssembly expects, but by LLVM convention they're uppercase and suffixed with their type after an underscore. Leave the C++ code that way, but print outt he names WebAssembly expects (lowercase, no type). We could teach tablegen to do this later, maybe by using `!cast<string>(node)` in the .td files. Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11776 llvm-svn: 244305
* ValueMapper: Resolve uniquing cycles more aggressivelyDuncan P. N. Exon Smith2015-08-071-9/+14
| | | | | | | | | | | | As a follow-up to r244181, resolve uniquing cycles underneath distinct nodes on the fly. This prevents uniquing cycles in early operands from affecting later operands. It also removes an iteration through distinct nodes' operands. No real functional change here, just more prompt resolution of temporary nodes. llvm-svn: 244302
* ValueMapper: Pull out helper to resolve cycles, NFCDuncan P. N. Exon Smith2015-08-071-8/+10
| | | | | | | Pull out a helper for resolving uniquing cycles of `Metadata` to remove the boiler-plate of downcasting to `MDNode`. llvm-svn: 244301
* MIR Serialization: Fix serialization of unnamed IR block references.Alex Lorenz2015-08-062-11/+33
| | | | | | | | The block address machine operands can reference IR blocks in other functions. This commit fixes a bug where the references to unnamed IR blocks in other functions weren't serialized correctly. llvm-svn: 244299
* MIR Parser: Simplify the token's string value handling.Alex Lorenz2015-08-063-56/+67
| | | | | | | | | | | | | | | | | This commit removes the 'StringOffset' and 'HasStringValue' fields from the MIToken struct and simplifies the 'stringValue' method which now returns the new 'StringValue' field. This commit also adopts a different way of initializing the lexed tokens - instead of constructing a new MIToken instance, the lexer resets the old token using the new 'reset' method and sets its attributes using the new 'setStringValue', 'setOwnedStringValue', and 'setIntegerValue' methods. Reviewers: Sean Silva Differential Revision: http://reviews.llvm.org/D11792 llvm-svn: 244295
* [AArch64][FastISel] Always use AND before checking the branch flag.Juergen Ributzka2015-08-061-1/+5
| | | | | | | | | | | | | When we are not emitting the condition for the branch, because the condition is in another BB or SDAG did the selection for us, then we have to mask the flag in the register with AND. This is required when the condition comes from a truncate, because SDAG only truncates down to a legal size of i32. This fixes rdar://problem/22161062. llvm-svn: 244291
* Revert "[AArch64][FastISel] Add more truncation tests." and ↵Juergen Ributzka2015-08-061-24/+31
| | | | | | | | | | | "[AArch64][FastISel] Always use an AND instruction when truncating to non-legal types." This reverts commit r243198 and 243304. Turns out this wasn't the correct fix for this problem. It works only within FastISel, but fails when the truncate is selected by SDAG. llvm-svn: 244287
* Revert accidentally committed WinEHPrepare changesDavid Majnemer2015-08-062-374/+9
| | | | | | This reverts commit r244272, r244273, r244274, and r244275. llvm-svn: 244278
* [IR] Remove TerminateInst's "NameStr" argumentDavid Majnemer2015-08-061-11/+7
| | | | | | | TerminateInst can't have a name because it doesn't produce a result. No functionality change is intended, this is just a cleanup. llvm-svn: 244276
* PHIs don't need to be postprocessedDavid Majnemer2015-08-061-31/+6
| | | | llvm-svn: 244275
* Handle PHI nodes prefacing EH pads tooDavid Majnemer2015-08-062-14/+88
| | | | llvm-svn: 244274
* handle phi nodesDavid Majnemer2015-08-061-4/+27
| | | | llvm-svn: 244273
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