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* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-16114-0/+28329
| | | | llvm-svn: 160270
* [asan] initialize asan error callbacks in runOnModule instead of doing that ↵Kostya Serebryany2012-07-161-8/+20
| | | | | | on-demand llvm-svn: 160269
* Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem2012-07-161-0/+7
| | | | | | | | | | | | undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160260
* Revert r160254 temporarily.Chandler Carruth2012-07-161-16/+16
| | | | | | | | | | | | It turns out that ASan relied on the at-the-end block insertion order to (purely by happenstance) disable some LLVM optimizations, which in turn start firing when the ordering is made more "normal". These optimizations in turn merge many of the instrumentation reporting calls which breaks the return address based error reporting in ASan. We're looking at several different options for fixing this. llvm-svn: 160256
* Teach AddressSanitizer to create basic blocks in a more natural order.Chandler Carruth2012-07-161-16/+16
| | | | | | | | | This is particularly useful to the backend code generators which try to process things in the incoming function order. Also, cleanup some uses of IRBuilder to be a bit simpler and more clear. llvm-svn: 160254
* This CL changes the function prologue and epilogue emitted on X86 when stack ↵Alexey Samsonov2012-07-161-53/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | needs realignment. It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. llvm-svn: 160248
* Move llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completesChandler Carruth2012-07-152-2/+2
| | | | | | | | | | | | the move of *Builder classes into the Core library. No uses of this builder in Clang or DragonEgg I could find. If there is a desire to have an IR-building-support library that contains all of these builders, that can be easily added, but currently it seems likely that these add no real overhead to VMCore. llvm-svn: 160243
* Move llvm/Support/MDBuilder.h to llvm/MDBuilder.h, to live withChandler Carruth2012-07-152-5/+5
| | | | | | | | | | | IRBuilder, DIBuilder, etc. This is the proper layering as MDBuilder can't be used (or implemented) without the Core Metadata representation. Patches to Clang and Dragonegg coming up. llvm-svn: 160237
* Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be ↵Nadav Rotem2012-07-152-1/+10
| | | | | | | | wider than the output element type. Make sure to trunc them if needed. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160235
* Teach getTargetVShiftNode about TargetConstant nodes.Nadav Rotem2012-07-151-1/+4
| | | | llvm-svn: 160234
* Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem2012-07-152-3/+8
| | | | | | | | | | Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot. PR12782. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160230
* Refactor the code that checks that all operands of a node are UNDEFs.Nadav Rotem2012-07-152-13/+28
| | | | | | | | | Add a micro-optimization to getNode of CONCAT_VECTORS when both operands are undefs. Can't find a testcase for this because VECTOR_SHUFFLE already handles undef operands, but Duncan suggested that we add this. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160229
* Reapply r160194, switching to use LV information for finding local kills.Chandler Carruth2012-07-151-56/+32
| | | | | | | | | | | | | | | | | | | | | The notable fix is to look at any dependencies attached to the kill instruction (or other instructions between MI nad the kill) where the dependencies are specific to the register in question. The old code implicitly handled this by rejecting the transform if *any* other uses were found within the block, but after the start point. The new code directly finds the kill, and has to re-use the existing dependency scan to check for non-kill uses. This was caught by self-host, but I found the bug via inspection and use of absurd assert scaffolding to compute the kills in two ways and compare them. So I have no useful testcase for this other than "bootstrap". I'd work harder to reduce a test case if this particular code were likely to live for a long time. Thanks to Benjamin Kramer for reviewing the fix itself. llvm-svn: 160228
* AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ↵Nadav Rotem2012-07-141-1/+7
| | | | | | | | vector with the same element type as the input vector. This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions. llvm-svn: 160222
* Add a dagcombine optimization to convert concat_vectors of undefs into a ↵Nadav Rotem2012-07-141-0/+11
| | | | | | | | single undef. The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node. llvm-svn: 160221
* Account for early-clobber reload instructions.Jakob Stoklund Olesen2012-07-141-0/+4
| | | | | | No test case, there are no in-tree targets that require this. llvm-svn: 160219
* Be more verbose when detecting dominance problems.Jakob Stoklund Olesen2012-07-132-7/+29
| | | | | | | | | | Catch uses of undefined physregs that haven't been added to basic block live-in lists. Run the verifier to pinpoint the problem. Also run the verifier when a virtual register use is not jointly dominated by defs. llvm-svn: 160207
* LSR Fix: check SCEV expression safety before expansion.Andrew Trick2012-07-132-1/+42
| | | | | | | | | | All SCEV expressions used by LSR formulae must be safe to expand. i.e. they may not contain UDiv unless we can prove nonzero denominator. Fixes PR11356: LSR hoists UDiv. llvm-svn: 160205
* IVUsers should only generate SCEV's for values that are safe to speculate.Andrew Trick2012-07-131-0/+7
| | | | | | | | | | This allows SCEVExpander to run on the IV expressions. This codifies an assumption made by LSR to complete the fix for PR11356, but I haven't been able to generate a separate unit test for this part. I'm adding it as an extra safety check. llvm-svn: 160204
* Factor SCEV traversal code so I can use it elsewhere. No functionality.Andrew Trick2012-07-131-51/+19
| | | | llvm-svn: 160203
* This is one of the first steps at moving to replace target-dependent Joel Jones2012-07-132-1/+26
| | | | | | | | | | | | | | | | | | | | intrinsics with target-indepdent intrinsics. The first instruction(s) to be handled are the vector versions of count leading zeros (ctlz). The changes here are to clang so that it generates a target independent vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector ctlzs with target-independent ctlzs. There are also changes to an existing test case in llvm for ARM vector count instructions and a new test for the bitcode upgrade. <rdar://problem/11831778> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> llvm-svn: 160200
* Revert r160194, which switched to use LV information for finding localChandler Carruth2012-07-131-19/+54
| | | | | | | | kills. This is causing miscompiles that I'm working on tracking down. llvm-svn: 160196
* Use the LiveVariables information to efficiently get local kills. ThisChandler Carruth2012-07-131-54/+19
| | | | | | | | | | removes the largest scaling problem in the test cases from PR13225 when ASan is switched to insert basic blocks in the natural CFG order. It may also solve some scaling problems for more normal code with large numbers of basic blocks and variables. llvm-svn: 160194
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-1311-46/+44
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189
* Remove variable_ops from ARM call instructions.Jakob Stoklund Olesen2012-07-133-22/+19
| | | | | | | | | | | | Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
* The Mips specific relocation R_MIPS_GOT_DISP Jack Carter2012-07-134-4/+12
| | | | | | | | | | is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. llvm-svn: 160183
* Make helper functions static.Benjamin Kramer2012-07-132-2/+2
| | | | llvm-svn: 160173
* Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.Craig Topper2012-07-131-2/+2
| | | | llvm-svn: 160162
* Fixed few warnings; trimmed empty lines.Galina Kistanova2012-07-131-123/+151
| | | | llvm-svn: 160159
* Provide function name in 'Cannot select' fatal error.Jim Grosbach2012-07-131-0/+1
| | | | | | | | | When dumping the DAG for a fatal 'Cannot select' back-end error, also provide the name of the function the construct is in. Useful when dealing with large testcases, as the next step is to llvm-extract the function in question to get a small(er) testcase. llvm-svn: 160152
* The end of the prologue should be marked with is_stmt.Eric Christopher2012-07-121-1/+1
| | | | | | | | Fixes PR13303. Patch by Paul Robinson! llvm-svn: 160148
* Fixed few warnings.Galina Kistanova2012-07-123-7/+10
| | | | llvm-svn: 160142
* Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ↵Benjamin Kramer2012-07-122-4/+5
| | | | | | | | MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. llvm-svn: 160137
* Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer2012-07-123-3/+49
| | | | | | | | | The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. llvm-svn: 160117
* The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type ofDuncan Sands2012-07-121-0/+10
| | | | | | | | | the input vector, it can be bigger (this is helpful for powerpc where <2 x i16> is a legal vector type but i16 isn't a legal type, IIRC). However this wasn't being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220. Lightly tweaked version of a patch by Michael Liao. llvm-svn: 160116
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-124-16/+44
| | | | | | myself and Manman Ren. llvm-svn: 160110
* Instcombine was transforming:Evan Cheng2012-07-121-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, -1 %and = and i64 %sub, %shr ret i64 %and to: %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, 2305843009213693951 %and = and i64 %sub, %shr ret i64 %and The demanded bit optimization is actually a pessimization because add -1 would be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization to check for negated constant to make sure it is actually reducing the width of the constant. rdar://11793464 llvm-svn: 160101
* TableGen: Location information for diagnostic.Jim Grosbach2012-07-121-1/+1
| | | | | | | | | | | def Pat<...>; Results in 'record name is not a string!' diagnostic. Not the best, but the lack of location information moves it from not very helpful into completely useless. We're in the Record class when throwing the error, so just add the location info directly. llvm-svn: 160098
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
| | | | llvm-svn: 160093
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-111-9/+14
| | | | | | | | It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. llvm-svn: 160090
* Patch for Mips direct object generation.Jack Carter2012-07-111-0/+8
| | | | | | | | | | | | | | | | | When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. llvm-svn: 160084
* This change removes an "initialization" warning.Jack Carter2012-07-111-4/+3
| | | | | | | | Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. llvm-svn: 160081
* In MemoryBuffer::getOpenFile() don't verify that the mmap'edArgyrios Kyrtzidis2012-07-111-10/+0
| | | | | | | | | | | | file buffer is null-terminated. If the file is smaller than we thought, mmap will not allow dereferencing past the pages that are enough to cover the actual file size, even though we asked for a larger address range. rdar://11612916 llvm-svn: 160075
* In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka2012-07-111-99/+114
| | | | | | | | order of binary encoding. Patch by Vladimir Medic. llvm-svn: 160073
* [x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier2012-07-111-1/+8
| | | | | | comments. llvm-svn: 160069
* X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren2012-07-111-1/+22
| | | | | | | When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. llvm-svn: 160066
* Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka2012-07-112-3/+17
| | | | llvm-svn: 160064
* InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng2012-07-111-1/+2
| | | | | | | | | | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to a copy: r1026 = copy r1024 This is correct. However it uses TII->isCoalescableExtInstr() which can return true for instructions which essentially does a sext_in_reg so this can end up with an illegal copy where the source and destination register classes do not match. Add a check to avoid it. Sorry, no test case possible at this time. rdar://11849816 llvm-svn: 160059
* PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.Benjamin Kramer2012-07-111-1/+1
| | | | | | This caused 6 of 65k possible 8 bit udivs to be wrong. llvm-svn: 160058
* [x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier2012-07-111-1/+1
| | | | | | to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. llvm-svn: 160055
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