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* [X86] When optimizing for minsize, use POP for small post-call stack clean-upMichael Kuperstein2015-08-112-1/+73
| | | | | | | | | | | | | | | | When optimizing for size, replace "addl $4, %esp" and "addl $8, %esp" following a call by one or two pops, respectively. We don't try to do it in general, but only when the stack adjustment immediately follows a call - which is the most common case. That allows taking a short-cut when trying to find a free register to pop into, instead of a full-blown liveness check. If the adjustment immediately follows a call, then every register the call clobbers but doesn't define should be dead at that point, and can be used. Differential Revision: http://reviews.llvm.org/D11749 llvm-svn: 244578
* Allow PeepholeOptimizer to fold a few more casesMichael Kuperstein2015-08-111-5/+4
| | | | | | | | | | The condition for clearing the folding candidate list was clamped together with the "uninteresting instruction" condition. This is too conservative, e.g. we don't need to clear the list when encountering an IMPLICIT_DEF. Differential Revision: http://reviews.llvm.org/D11591 llvm-svn: 244577
* [GMR] Be a bit smarter about which globals don't alias when doing recursive ↵Michael Kuperstein2015-08-111-7/+23
| | | | | | | | | | lookups Should hopefully fix the remainder of PR24288. Differential Revision: http://reviews.llvm.org/D11900 llvm-svn: 244575
* [RuntimeDyld][AArch64] Add explicit addends before calling relocationValueRef.Lang Hames2015-08-111-5/+4
| | | | | | relocationValueRef uses the addend, so it has to be set before the call. llvm-svn: 244574
* Fix unused variable 'X' in release builds.Nick Lewycky2015-08-111-0/+2
| | | | llvm-svn: 244571
* WebAssembly: NFC fix release build break, unused variable.JF Bastien2015-08-111-0/+1
| | | | | | | | | | Summary: Caused by D11914, pointed out by blaikie. Subscribers: llvm-commits, jfb, dblaikie Differential Revision: http://reviews.llvm.org/D11929 llvm-svn: 244570
* [IR] Verify EH pad predecessorsDavid Majnemer2015-08-111-14/+51
| | | | | | | Make sure that an EH pad's predecessors are using their unwind edge to transfer control to the EH pad. llvm-svn: 244563
* WebAssembly: add basic floating-point testsJF Bastien2015-08-111-4/+8
| | | | | | | | | | Summary: I somehow forgot to add these when I added the basic floating-point opcodes. Also remove ceil/floor/trunc/nearestint for now, and add them only when properly tested. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11927 llvm-svn: 244562
* [libFuzzer] add -only_ascii flagKostya Serebryany2015-08-115-2/+28
| | | | llvm-svn: 244559
* [WinEHPrepare] Add rudimentary support for the new EH instructionsDavid Majnemer2015-08-112-9/+374
| | | | | | | | | | | | | | | | | | This adds somewhat basic preparation functionality including: - Formation of funclets via coloring basic blocks. - Cloning of polychromatic blocks to ensure that funclets have unique program counters. - Demotion of values used between different funclets. - Some amount of cleanup once we have removed predecessors from basic blocks. - Verification that we are left with a CFG that makes some amount of sense. N.B. Arguments and numbering still need to be done. Differential Revision: http://reviews.llvm.org/D11750 llvm-svn: 244558
* Explicitly clear the MI operand list when getInstruction() is called. Call ↵Cameron Esfahani2015-08-114-22/+2
| | | | | | | | | | | | | | MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler. Summary: Explicitly clear the MI operand list when getInstruction() is called. Reviewers: hfinkel, t.p.northover, hvarga, kparzysz, jyknight, qcolombet, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11665 llvm-svn: 244557
* Print vectorization analysis when loop hint is specified.Tyler Nowicki2015-08-112-18/+39
| | | | | | This patch and a relatec clang patch solve the problem of having to explicitly enable analysis when specifying a loop hint pragma to get the diagnostics. Passing AlwasyPrint as the pass name (see below) causes the front-end to print the diagnostic if the user has specified '-Rpass-analysis' without an '=<target-pass>’. Users of loop hints can pass that compiler option without having to specify the pass and they will get diagnostics for only those loops with loop hints. llvm-svn: 244555
* Moved LoopVectorizeHints and related functions before ↵Tyler Nowicki2015-08-111-270/+270
| | | | | | LoopVectorizationLegality and LoopVectorizationCostModel. llvm-svn: 244552
* WebAssembly: simply assert on SNaN and NaNs with payloadsJF Bastien2015-08-111-4/+5
| | | | | | | | | | Summary: convertToHexString doesn't represent them correctly at this point in time. This is a follow-up to sunfish's suggestion in D11914. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11925 llvm-svn: 244551
* Simplify processLoop() by moving loop hint verification into ↵Tyler Nowicki2015-08-111-26/+35
| | | | | | Hints::allowVectorization(). llvm-svn: 244550
* MIR Serialization: Serialize UsedPhysRegMask from the machine register info.Alex Lorenz2015-08-112-0/+46
| | | | | | | | | | | | This commit serializes the UsedPhysRegMask register mask from the machine register information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask to keep the output minimal. This commit also allows the MIR parser to infer this mask from the register mask operands if the machine function doesn't specify it. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244548
* use range-based for loops; NFCISanjay Patel2015-08-111-8/+2
| | | | llvm-svn: 244545
* [libFuzzer] don't crash if the condition in a switch has unusual type (e.g. i72)Kostya Serebryany2015-08-111-0/+3
| | | | llvm-svn: 244544
* [LAA] Change name from addRuntimeCheck to addRuntimeChecks, NFCAdam Nemet2015-08-113-6/+6
| | | | | | This was requested by Hal in D11205. llvm-svn: 244540
* MIR Parser: Report an error when a stack object is redefined.Alex Lorenz2015-08-101-2/+5
| | | | llvm-svn: 244536
* Add lduw and lwua aliases for SPARCv9.Joerg Sonnenberger2015-08-101-0/+3
| | | | llvm-svn: 244535
* MIR Parser: Report an error when a fixed stack object is redefined.Alex Lorenz2015-08-101-2/+6
| | | | llvm-svn: 244534
* Load/store for float registers from/to alternate space.Joerg Sonnenberger2015-08-101-6/+6
| | | | llvm-svn: 244532
* use range-based for loop; NFCISanjay Patel2015-08-101-5/+5
| | | | llvm-svn: 244531
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-104-0/+47
| | | | llvm-svn: 244529
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-3/+1
| | | | llvm-svn: 244528
* [LoopVer] Remove unused pointer partition argument, NFC.Adam Nemet2015-08-101-2/+1
| | | | llvm-svn: 244527
* Extend late diagnostics to include late test for runtime pointer checks.Tyler Nowicki2015-08-102-14/+38
| | | | | | This patch moves checking the threshold of runtime pointer checks to the vectorization requirements (late diagnostics) and emits a diagnostic that infroms the user the loop would be vectorized if not for exceeding the pointer-check threshold. Clang will also append the options that can be used to allow vectorization. llvm-svn: 244523
* WebAssembly: print immediatesJF Bastien2015-08-103-20/+42
| | | | | | | | | | | | | | | Summary: For now output using C99's hexadecimal floating-point representation. This patch also cleans up how machine operands are printed: instead of special-casing per type of machine instruction, the code now handles operands generically. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11914 llvm-svn: 244520
* Add support for the signx instrution alias of SPARCv9.Joerg Sonnenberger2015-08-101-0/+5
| | | | llvm-svn: 244519
* NFC. Fix some format issues in lib/CodeGen/MachineBasicBlock.cpp.Cong Hou2015-08-101-11/+13
| | | | llvm-svn: 244518
* MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.Alex Lorenz2015-08-101-1/+4
| | | | | | | | | | | | The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
* remove function names from comments; NFCSanjay Patel2015-08-101-22/+20
| | | | llvm-svn: 244509
* StackMap: FastISel: Add an appropriate number of immediate operands to theAlex Lorenz2015-08-101-3/+6
| | | | | | | | | | | | | | | | | | frame setup instruction. This commit ensures that the stack map lowering code in FastISel adds an appropriate number of immediate operands to the frame setup instruction. The previous code added just one immediate operand, which was fine for a target like AArch64, but on X86 the ADJCALLSTACKDOWN64 instruction needs two explicit operands. This caused the machine verifier to report an error when the old code added just one. Reviewers: Juergen Ributzka Differential Revision: http://reviews.llvm.org/D11853 llvm-svn: 244508
* x86: Emit LAHF/SAHF instead of PUSHF/POPFJF Bastien2015-08-102-27/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's sandbox doesn't allow PUSHF/POPF out of security concerns (priviledged emulators have forgotten to mask system bits in the past, and EFLAGS's DF bit is a constant source of hilarity). Commit r220529 fixed PR20376 by saving cmpxchg's flags result using EFLAGS, this commit now generated LAHF/SAHF instead, for all of x86 (not just NaCl) because it leads to an overall performance gain over PUSHF/POPF. As with the previous patch this code generation is pretty bad because it occurs very later, after register allocation, and in many cases it rematerializes flags which were already available (e.g. already in a register through SETE). Fortunately it's somewhat rare that this code needs to fire. I did [[ https://github.com/jfbastien/benchmark-x86-flags | a bit of benchmarking ]], the results on an Intel Haswell E5-2690 CPU at 2.9GHz are: | Time per call (ms) | Runtime (ms) | Benchmark | | 0.000012514 | 6257 | sete.i386 | | 0.000012810 | 6405 | sete.i386-fast | | 0.000010456 | 5228 | sete.x86-64 | | 0.000010496 | 5248 | sete.x86-64-fast | | 0.000012906 | 6453 | lahf-sahf.i386 | | 0.000013236 | 6618 | lahf-sahf.i386-fast | | 0.000010580 | 5290 | lahf-sahf.x86-64 | | 0.000010304 | 5152 | lahf-sahf.x86-64-fast | | 0.000028056 | 14028 | pushf-popf.i386 | | 0.000027160 | 13580 | pushf-popf.i386-fast | | 0.000023810 | 11905 | pushf-popf.x86-64 | | 0.000026468 | 13234 | pushf-popf.x86-64-fast | Clearly `PUSHF`/`POPF` are suboptimal. It doesn't really seems to be worth teaching LLVM about individual flags, at least not for this purpose. Reviewers: rnk, jvoung, t.p.northover Subscribers: llvm-commits Differential revision: http://reviews.llvm.org/D6629 llvm-svn: 244503
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-5/+2
| | | | llvm-svn: 244499
* [InstCombine] Move SSE2/AVX2 arithmetic vector shift folding to instcombinerSimon Pilgrim2015-08-102-51/+31
| | | | | | | | As discussed in D11760, this patch moves the (V)PSRA(WD) arithmetic shift-by-constant folding to InstCombine to match the logical shift implementations. Differential Revision: http://reviews.llvm.org/D11886 llvm-svn: 244495
* Late evaluation of the fast-math vectorization requirement.Tyler Nowicki2015-08-104-7/+84
| | | | | | This patch moves the verification of fast-math to just before vectorization is done. This way we can tell clang to append the command line options would that allow floating-point commutativity. Specifically those are enableing fast-math or specifying a loop hint. llvm-svn: 244489
* Modify diagnostic messages to clearly indicate the why interleaving wasn't done.Tyler Nowicki2015-08-101-22/+69
| | | | | | Sometimes interleaving is not beneficial, as determined by the cost-model and sometimes it is disabled by a loop hint (by the user). This patch modifies the diagnostic messages to make it clear why interleaving wasn't done. llvm-svn: 244485
* [Sparc] Implement i64 load/store support for 32-bit sparc.James Y Knight2015-08-1011-49/+540
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LDD/STD instructions can load/store a 64bit quantity from/to memory to/from a consecutive even/odd pair of (32-bit) registers. They are part of SparcV8, and also present in SparcV9. (Although deprecated there, as you can store 64bits in one register). As recommended on llvmdev in the thread "How to enable use of 64bit load/store for 32bit architecture" from Apr 2015, I've modeled the 64-bit load/store operations as working on a v2i32 type, rather than making i64 a legal type, but with few legal operations. The latter does not (currently) work, as there is much code in llvm which assumes that if i64 is legal, operations like "add" will actually work on it. The same assumption does not hold for v2i32 -- for vector types, it is workable to support only load/store, and expand everything else. This patch: - Adds a new register class, IntPair, for even/odd pairs of registers. - Modifies the list of reserved registers, the stack spilling code, and register copying code to support the IntPair register class. - Adds support in AsmParser. (note that in asm text, you write the name of the first register of the pair only. So the parser has to morph the single register into the equivalent paired register). - Adds the new instructions themselves (LDD/STD/LDDA/STDA). - Hooks up the instructions and registers as a vector type v2i32. Adds custom legalizer to transform i64 load/stores into v2i32 load/stores and bitcasts, so that the new instructions can actually be generated, and marks all operations other than load/store on v2i32 as needing to be expanded. - Copies the unfortunate SelectInlineAsm hack from ARMISelDAGToDAG. This hack undoes the transformation of i64 operands into two arbitrarily-allocated separate i32 registers in SelectionDAGBuilder. and instead passes them in a single IntPair. (Arbitrarily allocated registers are not useful, asm code expects to be receiving a pair, which can be passed to ldd/std.) Also adds a bunch of test cases covering all the bugs I've added along the way. Differential Revision: http://reviews.llvm.org/D8713 llvm-svn: 244484
* [AArch64] Convert a conditional check that will always be true to an assert. ↵Chad Rosier2015-08-101-6/+4
| | | | | | NFC. llvm-svn: 244479
* [IndVarSimplify] Make cost estimation in RewriteLoopExitValues smarterIgor Laevsky2015-08-102-49/+52
| | | | | | Differential Revision: http://reviews.llvm.org/D11687 llvm-svn: 244474
* Add new llvm.loop.unroll.enable metadata.Mark Heffernan2015-08-101-20/+40
| | | | | | | | | | | | | This change adds the unroll metadata "llvm.loop.unroll.enable" which directs the optimizer to unroll a loop fully if the trip count is known at compile time, and unroll partially if the trip count is not known at compile time. This differs from "llvm.loop.unroll.full" which explicitly does not unroll a loop if the trip count is not known at compile time. The "llvm.loop.unroll.enable" is intended to be added for loops annotated with "#pragma unroll". llvm-svn: 244466
* Typo. Move comment closer to relevant code. NFC.Chad Rosier2015-08-101-3/+4
| | | | llvm-svn: 244465
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-3/+1
| | | | llvm-svn: 244464
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-4/+1
| | | | llvm-svn: 244463
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-2/+1
| | | | llvm-svn: 244460
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-3/+1
| | | | llvm-svn: 244458
* Add missing include guard to FuzzerInternal.h, NFC.Yaron Keren2015-08-101-0/+6
| | | | llvm-svn: 244457
* Silence a sign mismatch warning; NFC.Aaron Ballman2015-08-101-1/+1
| | | | llvm-svn: 244452
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