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* [X86] Simplify some multiclasses by inheriting from similar ones. NFCCraig Topper2017-09-011-17/+9
| | | | llvm-svn: 312311
* [X86] Add a couple TODOs to the PMADD52 instrucions about missing commuting ↵Craig Topper2017-09-011-0/+3
| | | | | | opportunities. llvm-svn: 312310
* [X86] Add isel patterns for memory forms of FMA3 intrinsic instructionsCraig Topper2017-09-011-0/+17
| | | | llvm-svn: 312309
* [X86] Remove unnecessary COPY_TO_REGCLASS(VR128) from the output patterns ↵Craig Topper2017-09-011-4/+4
| | | | | | | | for FMA instrinsics. The instructions are already defined as writing a VR128 register. llvm-svn: 312308
* AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault2017-08-316-20/+73
| | | | llvm-svn: 312297
* [WebAssembly] Fix getSymbolValue() for data symbolsSam Clegg2017-08-311-1/+6
| | | | | | | | | | This is mostly a fix for the output of `llvm-nm` See Bug 34392: https://bugs.llvm.org//show_bug.cgi?id=34392 Differential Revision: https://reviews.llvm.org/D37359 llvm-svn: 312294
* [IR] Missing changes for r312289 (NFC).Eugene Zelenko2017-08-311-6/+13
| | | | llvm-svn: 312290
* [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-316-85/+187
| | | | | | warnings; other minor fixes. Also affected in files (NFC). llvm-svn: 312289
* [WebAssembly] Refactor load ISel tablegen patterns into classesDerek Schuff2017-08-312-327/+215
| | | | | | | | | Not all of these will be able to be used by atomics because tablegen, but it still seems like a good change by itself. Differential Revision: https://reviews.llvm.org/D37345 llvm-svn: 312287
* [WebAssembly] Validate exports when parsing object filesSam Clegg2017-08-311-0/+8
| | | | | | | | Subscribers: jfb, dschuff, jgravelle-google, aheejin Differential Revision: https://reviews.llvm.org/D37358 llvm-svn: 312286
* [X86] Don't pull carry through X86ISD::ADD carryin, -1 if we can't guranteed ↵Craig Topper2017-08-311-22/+45
| | | | | | | | | | | | | | | | we're really using the carry flag from the add. Prior to this patch we had a DAG combine that tried to bypass an X86ISD::ADD with -1 being added to the carry flag of some previous operation. We would then pass the carry flag directly to user. But this is only safe if the user is looking for the carry flag and not the zero flag. So we need to only do this combine in a context where we know what flag the consumer is using. Fixes PR34381. Differential Revision: https://reviews.llvm.org/D37317 llvm-svn: 312285
* AMDGPU: Turn int pack pattern into build_vectorMatt Arsenault2017-08-312-1/+18
| | | | | | | | | | build_vector is a more useful canonical form when pattern matching packed operations, so turn shift into high element into a build_vector. Should show no change for now. llvm-svn: 312282
* [MachineOutliner] Recommit r312194, missed optimization remarksJessica Paquette2017-08-311-1/+36
| | | | | | | | | | | | | Before, this commit caused a buildbot failure: http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/6026/steps/test_llvm/logs/LLVM%20%3A%3A%20CodeGen__AArch64__machine-outliner-remarks.ll This was caused by the Key value in DiagnosticInfoOptimizationBase being deallocated before emitting the remarks defined in MachineOutliner.cpp. As of r312277 this should no longer be an issue. llvm-svn: 312280
* [llvm-pdbutil] Print detailed S_UDT stats.Zachary Turner2017-08-311-1/+5
| | | | | | | | | | | | | | This adds a new command line option, -udt-stats, which breaks down the stats of S_UDT records. These are one of the biggest contributors to the size of /DEBUG:FASTLINK PDBs, so they need some additional tools to be able to analyze their usage. This option will dig into each S_UDT record and determine what kind of record it points to, and then break down the statistics by the target type. The goal here is to identify how our object files differ from MSVC object files in S_UDT records, so that we can output fewer of them and reach size parity. llvm-svn: 312276
* [ObjCARC] Pass the correct BasicBlock to fix assertion failure.Akira Hatanaka2017-08-311-1/+2
| | | | | | | | | | The BasicBlock passed to FindPredecessorRetainWithSafePath should be the parent block of Autorelease. This fixes a crash that occurs in FindDependencies when StartInst is not in StartBB. rdar://problem/33866381 llvm-svn: 312266
* [DAGCombiner] Do a better job of ensuring we don't split elements when ↵Craig Topper2017-08-311-4/+7
| | | | | | combining an extract_subvector of a bitcasted build_vector. llvm-svn: 312253
* [InstCombine] improve demanded vector elements analysis of insertelementSanjay Patel2017-08-312-12/+11
| | | | | | | | | | | | | Recurse instead of returning on the first found optimization. Also, return early in the caller instead of continuing because that allows another round of simplification before we might potentially lose undef information from a shuffle mask by eliminating the shuffle. As noted in the review, we could probably do better and be more efficient by moving all of demanded elements into a separate pass, but this is yet another quick fix to instcombine. Differential Revision: https://reviews.llvm.org/D37236 llvm-svn: 312248
* [codeview] Generalize DIExpression parsing to handle load chainsReid Kleckner2017-08-314-42/+46
| | | | | | | | | | | | | | | Summary: Hopefully this also clarifies exactly when and why we're rewriting certiain S_LOCALs using reference types: We're using the reference type to stand in for a zero-offset load. Reviewers: inglorion Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37309 llvm-svn: 312247
* Revert r311525: "[XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove ↵Daniel Jasper2017-08-312-63/+63
| | | | | | | | synthetic references in .text" Breaks builds internally. Will forward repo instructions to author. llvm-svn: 312243
* [SLPVectorizer] Move out Entry->NeedToGather check and assert of inner loop ↵Dinar Temirbulatov2017-08-311-5/+6
| | | | | | as invariant, NFCI. llvm-svn: 312242
* [BinaryFormat] Fix out of bounds read.Benjamin Kramer2017-08-311-1/+1
| | | | | | | Found by OSS-FUZZ! https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3220 llvm-svn: 312238
* AMD family 17h (znver1) scheduler model update.Ashutosh Nema2017-08-311-3/+1550
| | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following: 1) Regex based Instruction itineraries for integer instructions. 2) The instructions are grouped as per the nature of the instructions (move, arithmetic, logic, Misc, Control Transfer). 3) FP instructions and their itineraries are added which includes values for SSE4A, BMI, BMI2 and SHA instructions. Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36617 llvm-svn: 312237
* [Object] Verify object sizes before handing out StringRefs pointing outBenjamin Kramer2017-08-311-12/+3
| | | | | | | | | of bounds. This can only happen on corrupt input. Found by OSS-FUZZ! https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3228 llvm-svn: 312235
* [GlobalISel][X86] Refactor X86LegalizerInfo. NFC.Igor Breger2017-08-311-45/+10
| | | | llvm-svn: 312234
* [AArch64] v8.3-a complex number supportSam Parker2017-08-315-0/+282
| | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. Differential Revision: https://reviews.llvm.org/D36792 llvm-svn: 312228
* [ARM] Reverse PostRASched subtarget feature logicSam Parker2017-08-314-24/+17
| | | | | | | | | | | | Replace the UsePostRAScheduler SubtargetFeature with DisablePostRAScheduler, which is then used by Swift and Cyclone. This patch maintains enabling PostRA scheduling for other Thumb2 capable cores and/or for functions which are being compiled in Arm mode. Differential Revision: https://reviews.llvm.org/D37055 llvm-svn: 312226
* [AArch64] IDSAR6 register assembler supportSam Parker2017-08-311-0/+3
| | | | | | | | | | The IDSAR6 system register has been introduced to identify the v8.3-a Javascript data type conversion and v8.2-a dot product support. Differential Revision: https://reviews.llvm.org/D37068 llvm-svn: 312225
* [AArch64] Support COFF linker directivesMartin Storsjo2017-08-311-0/+24
| | | | | | | | | | This is similar to what was done for ARM in SVN r269574; the code and the test are straight copypaste to the corresponding AArch64 code and test directory. Differential revision: https://reviews.llvm.org/D37204 llvm-svn: 312223
* [IRCE] Identify loops with latch comparison against current IV valueMax Kazantsev2017-08-311-11/+49
| | | | | | | | | | | | | | | Current implementation of parseLoopStructure interprets the latch comparison as a comarison against `iv.next`. If the actual comparison is made against the `iv` current value then the loop may be rejected, because this misinterpretation leads to incorrect evaluation of the latch start value. This patch teaches the IRCE to distinguish this kind of loops and perform the optimization for them. Now we use `IndVarBase` variable which can be either next or current value of the induction variable (previously we used `IndVarNext` which was always the value on next iteration). Differential Revision: https://reviews.llvm.org/D36215 llvm-svn: 312221
* Revert r312194: "[MachineOutliner] Add missed optimization remarks for the ↵Daniel Jasper2017-08-311-36/+1
| | | | | | | | | outliner." Breaks on buildbot: http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/6026/steps/test_llvm/logs/LLVM%20%3A%3A%20CodeGen__AArch64__machine-outliner-remarks.ll llvm-svn: 312219
* [IRCE][NFC] Rename IndVarNext to IndVarBaseMax Kazantsev2017-08-311-21/+21
| | | | | | | | | Renaming as a preparation step to generalizing IRCE for comparison not only against the next value of an indvar, but also against the current. Differential Revision: https://reviews.llvm.org/D36509 llvm-svn: 312215
* Temporarily revert "Update branch coalescing to be a PowerPC specific pass"Eric Christopher2017-08-317-63/+41
| | | | | | | | From comments and code review it wasn't intended to be enabled by default yet. This reverts commit r311588. llvm-svn: 312214
* AMDGPU: Don't assert in TTI with fp32 denorms enabledMatt Arsenault2017-08-311-3/+25
| | | | | | Also refine for f16 and rcp cases. llvm-svn: 312213
* Revert "llvm-mt: Fix release of OutputDoc"Vitaly Buka2017-08-311-3/+1
| | | | | | | | Multiple bots are broken. This reverts commit r312207. llvm-svn: 312212
* llvm-mt: Fix release of OutputDocVitaly Buka2017-08-311-1/+3
| | | | | | | | | | | | | | | Summary: xmlDoc needs to be released with xmlFreeDoc. Reset root element before release to avoid release of CombinedRoot owned by CombinedDoc, Reviewers: ecbeckmann, rnk, zturner, ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37321 llvm-svn: 312207
* AMDGPU: Use set for tracked registersMatt Arsenault2017-08-311-20/+23
| | | | | | | | | | | | | | | The majority of the time spent in the pass checking for the register reads. Rather than searching all of the defined registers for uses in each instruction, use a set of defined registers and check the operands of the instruction. This process still is algorithmically not great, but with the additional trick of skipping the analysis for addresses with one use, this brings one slow testcase into a reasonable range. llvm-svn: 312206
* [Orc] Add a comment about member variable dependencies to OrcMCJITReplacement.Lang Hames2017-08-311-0/+3
| | | | | | | | | The comment explains the reason behind the change in member variable order in r312086. Thanks to Philip Reames for the suggestion. llvm-svn: 312205
* Revert "Revert r312139 "Verifier: Verify the correctness of fragment ↵Adrian Prantl2017-08-311-8/+22
| | | | | | | | expressions attached to globals."" This reverts commit r312182 after fixing PR34390. llvm-svn: 312197
* Don't add a fragment expression when GlobalSRA splits up a single-member structAdrian Prantl2017-08-311-9/+12
| | | | | | | | Fixes PR34390. https://bugs.llvm.org/show_bug.cgi?id=34390 llvm-svn: 312196
* [MachineOutliner] Add missed optimization remarks for the outliner.Jessica Paquette2017-08-301-1/+36
| | | | | | | | | | | | | | This adds missed optimization remarks which report viable candidates that were not outlined because they would increase code size. Other remarks will come in separate commits. This will help to diagnose code size regressions and changes in outliner behaviour in projects using the outliner. https://reviews.llvm.org/D37085 llvm-svn: 312194
* [yaml2obj][ELF] Make symbols optional for relocationsPetr Hosek2017-08-301-1/+1
| | | | | | | | | | | | | | | | Some kinds of relocations do not have symbols, like R_X86_64_RELATIVE for instance. I would like to test this case in D36554 but currently can't because symbols are required by yaml2obj. The other option is using the empty symbol but that doesn't seem quite right to me. This change makes the Symbol field of Relocation optional and in the case where the user does not specify a symbol name the Symbol index is 0. Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D37276 llvm-svn: 312192
* [X86] Remove some code from fast isel that is no longer needed with i1 being ↵Craig Topper2017-08-301-31/+0
| | | | | | an illegal type. llvm-svn: 312190
* [SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzerMatt Morehouse2017-08-301-9/+21
| | | | | | | | | | | | | | | | | | Summary: - Don't sanitize __sancov_lowest_stack. - Don't instrument leaf functions. - Add CoverageStackDepth to Fuzzer and FuzzerNoLink. - Only enable on Linux. Reviewers: vitalybuka, kcc, george.karpenkov Reviewed By: kcc Subscribers: kubamracek, cfe-commits, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37156 llvm-svn: 312185
* Revert r312139 "Verifier: Verify the correctness of fragment expressions ↵Hans Wennborg2017-08-301-22/+8
| | | | | | | | attached to globals." This caused PR34390. llvm-svn: 312182
* [ARM] Replace fixed-size SmallSet with a bitset.Benjamin Kramer2017-08-301-30/+30
| | | | | | It's smaller. No functionality change. llvm-svn: 312180
* AMDGPU: Correct operand types for v_mad_mix*Matt Arsenault2017-08-304-13/+37
| | | | | | | | | | | | These aren't really packed instructions, so the default op_sel_hi should be 0 since this indicates a conversion. The operand types are scalar values that behave similar to an f16 scalar that may be converted to f32. Doesn't change the default printing for op_sel_hi, just the parsing. llvm-svn: 312179
* Revert r312154 "Re-enable "[MachineCopyPropagation] Extend pass to do COPY ↵Hans Wennborg2017-08-303-577/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | source forwarding"" It caused PR34387: Assertion failed: (RegNo < NumRegs && "Attempting to access record for invalid register number!") > Issues identified by buildbots addressed since original review: > - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. > - The pass no longer forwards COPYs to physical register uses, since > doing so can break code that implicitly relies on the physical > register number of the use. > - The pass no longer forwards COPYs to undef uses, since doing so > can break the machine verifier by creating LiveRanges that don't > end on a use (since the undef operand is not considered a use). > > [MachineCopyPropagation] Extend pass to do COPY source forwarding > > This change extends MachineCopyPropagation to do COPY source forwarding. > > This change also extends the MachineCopyPropagation pass to be able to > be run during register allocation, after physical registers have been > assigned, but before the virtual registers have been re-written, which > allows it to remove virtual register COPY LiveIntervals that become dead > through the forwarding of all of their uses. llvm-svn: 312178
* Simplify writeArchive return type.Rui Ueyama2017-08-303-17/+13
| | | | | | | | | | writeArchive returned a pair, but the first element of the pair is always its first argument on failure, so it doesn't make sense to return it from the function. This patch change the return type so that it does't return it. Differential Revision: https://reviews.llvm.org/D37313 llvm-svn: 312177
* SelectionDAG: Emit correct debug info for multi-register function arguments.Adrian Prantl2017-08-301-0/+21
| | | | | | | | | Previously we would just describe the first register and then call it quits. This patch emits fragment expressions for each register. <rdar://problem/34075307> llvm-svn: 312169
* [IR] Don't print "!DIExpression() = !DIExpression()" when dumpingReid Kleckner2017-08-301-1/+1
| | | | | | | | | Now that we print DIExpressions inline everywhere, we don't need to print them once as an operand and again as a value. This is only really visible when calling dump() or print() directly on a DIExpression during debugging. llvm-svn: 312168
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