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* Use llvm:Twine instead of std::to_string.Chaoren Lin2016-04-283-11/+11
| | | | | | | | | | | | std::to_string is not available from the Android NDK. Reviewers: lhames, ovyalov, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19638 llvm-svn: 267829
* [SystemZ] Support Swift Calling ConventionBryan Chan2016-04-284-3/+31
| | | | | | | | | | | | | | | | Summary: Port rL265480, rL264754, rL265997 and rL266252 to SystemZ, in order to enable the Swift port on the architecture. SwiftSelf and SwiftError are assigned to R10 and R9, respectively, which are normally callee-saved registers. For more information, see: RFC: Implementing the Swift calling convention in LLVM and Clang https://groups.google.com/forum/#!topic/llvm-dev/epDd2w93kZ0 Reviewers: kbarton, manmanren, rjmccall, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19414 llvm-svn: 267823
* LTO: Don't bother trying to mangle unnamed globals, as they can't be ↵Peter Collingbourne2016-04-271-0/+4
| | | | | | | | | | | | | | preserved with MustPreserveSymbols. Summary: Should fix sanitizer-windows bot. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19635 llvm-svn: 267820
* Parse module information from DBI stream.Zachary Turner2016-04-273-2/+161
| | | | | | | | | | | | This gets more data out of the DBI strema of the PDB. In particular it extracts the metadata for the list of modules (compilands) that this PDB contains info about, and adds support for dumping these fields to llvm-pdbdump. Differential Revision: http://reviews.llvm.org/D19570 Reviewed By: ruiu llvm-svn: 267818
* [ImplicitNullChecks] Properly update the live-in of the block of the memory ↵Quentin Colombet2016-04-271-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | operation. We basically replace: HoistBB: cond_br NullBB, NotNullBB NullBB: ... NotNullBB: <reg> = load into HoistBB <reg> = load_faulting_op NullBB uncond_br NotNullBB NullBB: ... NotNullBB: ## <reg> is now live-in of NotNullBB ... This partially fixes the machine verifier error for test/CodeGen/X86/implicit-null-check.ll, but it still fails because of the implicit CFG structure. llvm-svn: 267817
* [PGO] Promote indirect calls to conditional direct calls with value-profileRong Xu2016-04-274-1/+705
| | | | | | | | | | This patch implements the transformation that promotes indirect calls to conditional direct calls when the indirect-call value profile meta-data is available. Differential Revision: http://reviews.llvm.org/D17864 llvm-svn: 267815
* [SimplifyCFG] propagate branch metadata when creating selectSanjay Patel2016-04-271-2/+2
| | | | | | | | There's no existing test for this path, and I don't know how to expose it in a regression test, but I'm assuming there's some reason this path exists. llvm-svn: 267813
* [RuntimeDyld] Propagate another dropped error in RuntimeDyldELF.Lang Hames2016-04-271-1/+2
| | | | | | This should fix the PPC64 bots. llvm-svn: 267810
* [X86] Enable the post-RA-scheduler for clang's default 32-bit cpu.Mitch Bodart2016-04-272-12/+36
| | | | | | | | | For compilations with no explicit cpu specified, this exhibits nice gains on Silvermont, with neutral performance on big cores. Differential Revision: http://reviews.llvm.org/D19138 llvm-svn: 267809
* [X86][FastISel] Make sure we use the right register class when we select stores.Quentin Colombet2016-04-271-1/+9
| | | | llvm-svn: 267806
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-271-17/+69
| | | | | | new one. llvm-svn: 267798
* [X86] Fix the lowering of TLS calls.Quentin Colombet2016-04-272-6/+9
| | | | | | | | | | | The callseq_end node must be glued with the TLS calls, otherwise, the generic code will miss the uses of the returned value and will mark it dead. Moreover, TLSCall 64-bit pseudo must not set an implicit-use on RDI, the pseudo uses the symbol address at this point not RDI and the lowering will do the right thing. llvm-svn: 267797
* [MCAssembler] Allow backend to finalize layout post-relaxation.Colin LeMahieu2016-04-271-0/+1
| | | | | | Differential revision: http://reviews.llvm.org/D19429 llvm-svn: 267796
* [PGO] Prohibit address recording if the function is both internal and COMDATRong Xu2016-04-271-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D19515 llvm-svn: 267792
* AMDGPU: Account for globals in AMDGPUPromoteAlloca passMatt Arsenault2016-04-271-2/+4
| | | | | | Patch by Bas Nieuwenhuizen llvm-svn: 267791
* [RuntimeDyld] Add missing include - <string> is requried for std::to_string.Lang Hames2016-04-273-0/+3
| | | | | | | This should fix the compile error that showed up in build: http://lab.llvm.org:8011/builders/lldb-x86_64-ubuntu-14.04-buildserver/builds/6754/ llvm-svn: 267790
* [RuntimeDyld] Propagate Errors from findPPC64TOCSection.Lang Hames2016-04-271-3/+6
| | | | llvm-svn: 267789
* [ARM] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.Ahmed Bougacha2016-04-271-2/+2
| | | | | | | | | We run after PEI. Found via inspection; no obvious testcase. Follow-up to r266679. llvm-svn: 267781
* [AArch64] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.Ahmed Bougacha2016-04-271-2/+2
| | | | | | | | | We run after PEI. Found via inspection; no obvious testcase. Follow-up to r266339. llvm-svn: 267780
* [AArch64] Set correct successors in CMPXCHG pseudo expansion.Ahmed Bougacha2016-04-271-2/+4
| | | | | | | | | | | transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas it should be a successor of the original MBB. Follow-up to r266339. Unfortunately, it's tricky to catch this in the verifier. llvm-svn: 267779
* [ARM] Set correct successors in CMPXCHG pseudo expansion.Ahmed Bougacha2016-04-271-2/+4
| | | | | | | | | | | | | | transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas it should be a successor of the original MBB. The testcase changes are caused by Thumb2SizeReduction, which was previously confused by the broken CFG. Follow-up to r266679. Unfortunately, it's tricky to catch this in the verifier. llvm-svn: 267778
* [RuntimeDyld] Plumb Error/Expected through the internals of RuntimeDyld.Lang Hames2016-04-2713-288/+471
| | | | | | | | | | | | | Also replaces a number of calls to report_fatal_error with Error returns. The plumbing will make it easier to return errors originating in libObject. Replacing report_fatal_errors with Error returns will give JIT clients the opportunity to recover gracefully when the JIT is unable to produce/relocate code, as well as providing meaningful error messages that can be used to file bug reports. llvm-svn: 267776
* Fix build failure under NDEBUG.Than McIntosh2016-04-271-0/+4
| | | | llvm-svn: 267774
* [X86]: Quit promoting 16 bit loads to 32 bit.Kevin B. Smith2016-04-271-17/+0
| | | | | | Differential Revision: http://reviews.llvm.org/D19592 llvm-svn: 267773
* [libFuzzer] disable leak detection if we have tried it for 1000 times w/o ↵Kostya Serebryany2016-04-271-1/+2
| | | | | | finding a leak [part 2] llvm-svn: 267771
* [libFuzzer] disable leak detection if we have tried it for 1000 times w/o ↵Kostya Serebryany2016-04-274-0/+28
| | | | | | finding a leak llvm-svn: 267770
* Add optimization bisect opt-in calls for PowerPC passesAndrew Kaylor2016-04-279-3/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D19554 llvm-svn: 267769
* [CodeGenPrepare] Don't sink a cast past its userDavid Majnemer2016-04-271-0/+5
| | | | | | | | | | The sink cast machinery is supposed to sink casts as close to their user as possible. However, an EH pad is the first instruction in it's basic block. Don't sink if the user is an EH pad. This fixes PR27536. llvm-svn: 267767
* Refactor debugging code, NFC.Than McIntosh2016-04-271-31/+30
| | | | | | | | | | | | | | | | | Summary: Refactor debugging routines to reduce code duplication. Remove a couple of #include's that were not needed. Don't require MachineDominator as a prereq for this pass (not needed). These changes split off from http://reviews.llvm.org/D18827. Reviewers: wmi, gbiv, qcolombet Subscribers: llvm-commits, davidxl, jevinskie Differential Revision: http://reviews.llvm.org/D18992 llvm-svn: 267766
* [NVPTX] Run NVVMReflect at the beginning of IR passes.Justin Lebar2016-04-272-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently the NVVMReflect pass is run at the beginning of our backend passes. But really, it should be run as early as possible, as it's simply resolving an "if" statement in code. So copy it into TargetMachine::addEarlyAsPossiblePasses. We still run it at the beginning of the backend passes, since it's needed for correctness when lowering to nvptx. (Specifically, NVVMReflect changes each call to the __nvvm_reflect function or llvm.nvvm.reflect intrinsic into an integer constant, based on the pass's configuration. Clearly we miss many optimization opportunities if we perform this transformation at the beginning of codegen.) Reviewers: rnk Subscribers: tra, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D18616 llvm-svn: 267765
* [LIR] Set attributes on memset_pattern16.Ahmed Bougacha2016-04-271-0/+2
| | | | | | | | | "inferattrs" will deduce the attribute, but it will be too late for many optimizations. Set it ourselves when creating the call. Differential Revision: http://reviews.llvm.org/D17598 llvm-svn: 267762
* [LIR] Reuse variable. NFCI.Ahmed Bougacha2016-04-271-1/+1
| | | | llvm-svn: 267761
* [InferAttrs] Mark memset_pattern16 params nocapture.Ahmed Bougacha2016-04-271-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D19471 llvm-svn: 267760
* [TLI] Unify LibFunc attribute inference. NFCI.Ahmed Bougacha2016-04-272-795/+723
| | | | | | | | | | | | | Now the pass is just a tiny wrapper around the util. This lets us reuse the logic elsewhere (done here for BuildLibCalls) instead of duplicating it. The next step is to have something like getOrInsertLibFunc that also sets the attributes. Differential Revision: http://reviews.llvm.org/D19470 llvm-svn: 267759
* [TLI] Unify LibFunc signature checking. NFCI.Ahmed Bougacha2016-04-277-711/+583
| | | | | | | | | I tried to be as close as possible to the strongest check that existed before; cleaning these up properly is left for future work. Differential Revision: http://reviews.llvm.org/D19469 llvm-svn: 267758
* [TLI] Fix indentation. NFC.Ahmed Bougacha2016-04-271-1/+1
| | | | llvm-svn: 267757
* Clean up to avoid compiler warnings for casting away const qualifiers.Sjoerd Meijer2016-04-272-4/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D19598 llvm-svn: 267753
* Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ↵Chad Rosier2016-04-276-39/+13
| | | | | | | | SMRD." This reverts commit r267733 due to a -Werror,-Wunused-function error. llvm-svn: 267752
* [LV] Reallow positive-stride interleaved load groups with gapsMatthew Simpson2016-04-271-9/+47
| | | | | | | | | | | | | | We previously disallowed interleaved load groups that may cause us to speculatively access memory out-of-bounds (r261331). We did this by ensuring each load group had an access corresponding to the first and last member. Instead of bailing out for these interleaved groups, this patch enables us to peel off the last vector iteration, ensuring that we execute at least one iteration of the scalar remainder loop. This solution was proposed in the review of the previous patch. Differential Revision: http://reviews.llvm.org/D19487 llvm-svn: 267751
* [SLPVectorizer] Refactor where MinVecRegSize and MaxVecRegSize live.Arch D. Robison2016-04-271-20/+28
| | | | | | | | | This is the first of two commits for extending SLP Vectorizer to deal with aggregates. This commit merely refactors existing logic. http://reviews.llvm.org/D14185 llvm-svn: 267748
* [DAGCombiner] Follow coding convention for function name (NFC)Gerolf Hoflehner2016-04-273-4/+4
| | | | llvm-svn: 267745
* [Mips] Add support for llvm.thread.pointer intrinsic.Marcin Koscielnicki2016-04-271-0/+4
| | | | | | | | This will be used to implement __builtin_thread_pointer in clang. Differential Revision: http://reviews.llvm.org/D19569 llvm-svn: 267743
* Silence a -Wdangling-elseReid Kleckner2016-04-271-1/+2
| | | | llvm-svn: 267737
* Add parentheses to silence buildbot warningMatthew Simpson2016-04-271-2/+2
| | | | llvm-svn: 267734
* [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov2016-04-276-13/+39
| | | | | | | | | | | Added support of TTMP quads. Reworked M0 exclusion machinery for SMRD and similar instructions to enable usage of TTMP registers in those instructions as destinations. Tests added. Differential Revision: http://reviews.llvm.org/D19342 llvm-svn: 267733
* [PDB] Fix function names for private symbols in PDBsReid Kleckner2016-04-271-14/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: llvm-symbolizer wants to get linkage names of functions for historical reasons. Linkage names are only recorded in the PDB for public symbols, and the linkage name is apparently stored separately in some "public symbol" record. We had a workaround in PDBContext which would look for such symbols when the user requested linkage names. However, when given an address that was truly in a private function and public funciton, we would accidentally find nearby public symbols and return those function names. The fix is to look for both function symbols and public symbols and only prefer the public symbol name if the addresses of the symbols agree. Fixes PR27492 Reviewers: zturner Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19571 llvm-svn: 267732
* AMDGPU/SI: Add llvm.amdgcn.s.waitcnt.all intrinsicNicolai Haehnle2016-04-272-14/+78
| | | | | | | | | | | | | | | | | Summary: So it appears that to guarantee some of the ordering requirements of a GLSL memoryBarrier() executed in the shader, we need to emit an s_waitcnt. (We can't use an s_barrier, because memoryBarrier() may appear anywhere in the shader, in particular it may appear in non-uniform control flow.) Reviewers: arsenm, mareko, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19203 llvm-svn: 267729
* [TTI] Add hook for vector extract with extensionMatthew Simpson2016-04-274-3/+70
| | | | | | | | | | | | | | | This change adds a new hook for estimating the cost of vector extracts followed by zero- and sign-extensions. The motivating example for this change is the SMOV and UMOV instructions on AArch64. These instructions move data from vector to general purpose registers while performing the corresponding extension (sign-extend for SMOV and zero-extend for UMOV) at the same time. For these operations, TargetTransformInfo can assume the extensions are free and only report the cost of the vector extract. The SLP vectorizer has been updated to make use of the new hook. Differential Revision: http://reviews.llvm.org/D18523 llvm-svn: 267725
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware ↵Artem Tamazov2016-04-272-13/+42
| | | | | | | | | | | | registers. Possibility to specify code of hardware register kept. Disassemble to symbolic name, if name is known. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19335 llvm-svn: 267724
* Revert r267649, it caused PR27539.Nico Weber2016-04-272-147/+7
| | | | llvm-svn: 267723
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