| Commit message (Collapse) | Author | Age | Files | Lines |
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- Also, update the LangRef documentation on module flags to match the
implementation.
llvm-svn: 172498
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we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.
The bug was exposed by the SingleSourcetest case
DuffsDevice.c.
Contributer: Jack Carter
llvm-svn: 172496
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simply use the getParser method from MCAsmParserExtension, working through the
MCAsmParser interface. There's no longer a need to overload that method to
cast it to the concrete AsmParser.
llvm-svn: 172491
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This finally allows AsmParser to no longer list GenericAsmParser as a friend.
All member vars directly accessed by GenericAsmParser have been properly
encapsulated and exposed through the MCAsmParser interface. This reduces the
coupling between AsmParser and GenericAsmParser.
llvm-svn: 172490
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llvm-svn: 172489
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---------------------------------------------------------------------------
C_A: reassociation is allowed
C_R: reciprocal of a constant C is appropriate, which means
- 1/C is exact, or
- reciprocal is allowed and 1/C is neither a special value nor a denormal.
-----------------------------------------------------------------------------
rule1: (X/C1) / C2 => X / (C2*C1) (if C_A)
=> X * (1/(C2*C1)) (if C_A && C_R)
rule 2: X*C1 / C2 => X * (C1/C2) if C_A
rule 3: (X/Y)/Z = > X/(Y*Z) (if C_A && at least one of Y and Z is symbolic value)
rule 4: Z/(X/Y) = > (Z*Y)/X (similar to rule3)
rule 5: C1/(X*C2) => (C1/C2) / X (if C_A)
rule 6: C1/(X/C2) => (C1*C2) / X (if C_A)
rule 7: C1/(C2/X) => (C1/C2) * X (if C_A)
llvm-svn: 172488
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have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141
llvm-svn: 172484
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llvm-svn: 172483
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llvm-svn: 172481
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The included test case is derived from one of the GCC compatibility tests.
The problem arises after the selection DAG has been converted to type-legalized
form. The combiner first sees a 64-bit load that can be converted into a
pre-increment form. The original load feeds into a SRL that isolates the
upper 32 bits of the loaded doubleword. This looks like an opportunity for
DAGCombiner::ReduceLoadWidth() to replace the 64-bit load with a 32-bit load.
However, this transformation is not valid, as the replacement load is not
a pre-increment load. The pre-increment load produces an extra result,
which feeds a subsequent add instruction. The replacement load only has
one result value, and this value is propagated to all uses of the pre-
increment load, including the add. Because the add is looking for the
second result value as its operand, it ends up attempting to add a constant
to a token chain, resulting in a crash.
So the patch simply disables this transformation for any load with more than
two result values.
llvm-svn: 172480
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Refactor the big if/else sequence into one string switch for ARM subtype selection.
llvm-svn: 172475
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cortex-m0, cortex-m3, and cortex-m4 on the backend side.
Adds new subtype values for the MachO format and use them when the related triple are set.
llvm-svn: 172472
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Fix a casting-away-const compiler warning.
llvm-svn: 172471
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Do proper casting to eliminate a const-away-cast compiler warning.
llvm-svn: 172470
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Properly cast some more code that triggered cast-away-const errors.
llvm-svn: 172469
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Properly cast code to eliminate cast-away-const errors.
llvm-svn: 172468
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Add a const version of getFpValPtr to avoid a cast-away-const warning.
llvm-svn: 172467
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Fix another cast-away-const cast.
llvm-svn: 172466
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Stop a gcc warning about casting away const.
llvm-svn: 172465
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Note that this bug is only exposed because LTO fails to use TTI.
Fixes self-LTO of clang. rdar://13007381.
llvm-svn: 172462
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llvm-svn: 172460
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llvm-svn: 172452
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Now that it behaves itself in terms of streamer independence (r172450), this
method can be moved to MCAsmParser to be available to all extensions,
overriding, etc.
-- -This line, and those below, will be ignored--
M lib/MC/MCParser/AsmParser.cpp
M include/llvm/MC/MCParser/MCAsmParser.h
llvm-svn: 172451
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The aim of this patch is to fix the following piece of code in the
platform-independent AsmParser:
void AsmParser::CheckForValidSection() {
if (!ParsingInlineAsm && !getStreamer().getCurrentSection()) {
TokError("expected section directive before assembly directive");
Out.SwitchSection(Ctx.getMachOSection(
"__TEXT", "__text",
MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
0, SectionKind::getText()));
}
}
This was added for the "-n" option of llvm-mc.
The proposed fix adds another virtual method to MCStreamer, called
InitToTextSection. Conceptually, it's similar to the existing
InitSections which initializes all common sections and switches to
text. The new method is implemented by each platform streamer in a way
that it sees fit. So AsmParser can now do this:
void AsmParser::CheckForValidSection() {
if (!ParsingInlineAsm && !getStreamer().getCurrentSection()) {
TokError("expected section directive before assembly directive");
Out.InitToTextSection();
}
}
Which is much more reasonable.
llvm-svn: 172450
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Since it's used by extensions. One further step to fully decoupling
GenericAsmParser from an intimate knowledge of the internals of AsmParser,
pointing it to the MCASmParser interface instead (like all other parser
extensions do).
Since this change moves the MacroArgument type to the interface header, it's
renamed to be a bit more descriptive in a general context.
llvm-svn: 172449
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The methods are also exposed via the MCAsmParser interface, which allows more
than one client to control them. Previously, GenericAsmParser was playing with
a member var in AsmParser directly (by virtue of being its friend).
llvm-svn: 172440
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breaks the VS2008 build
llvm-svn: 172411
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than 2 arguments.
llvm-svn: 172379
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needing to specify everything twice. No functional change intended
llvm-svn: 172378
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llvm-svn: 172374
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use doxygen). Still some work to do though.
llvm-svn: 172371
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2x blocks each assigned a value via a phi-node causing each to depend on the other.
A test case is provided as well.
llvm-svn: 172368
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llvm-svn: 172364
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cache result of Size/OffsetVisitor to speedup analysis of PHI nodes
llvm-svn: 172363
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llvm-svn: 172358
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Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.
llvm-svn: 172353
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and i16).
llvm-svn: 172348
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llvm-svn: 172347
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llvm-svn: 172346
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case, but looking at the diff this was an obviously unintended change.
Thanks for the careful review Bill! =]
llvm-svn: 172336
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Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.
llvm-svn: 172322
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warning. [-Wunused-function]
llvm-svn: 172319
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Found by valgrind.
llvm-svn: 172318
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llvm-svn: 172315
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llvm-svn: 172299
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llvm-svn: 172298
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=> objc_autorelease but were not updating the InstructionClass to IC_Autorelease.
llvm-svn: 172288
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not be placed into an autorelease pool.
The reason that this occurs is that tail calling objc_autorelease eventually
tail calls -[NSObject autorelease] which supports fast autorelease. This can
cause us to violate the semantic gaurantees of __autoreleasing variables that
assignment to an __autoreleasing variables always yields an object that is
placed into the innermost autorelease pool.
The fix included in this patch works by:
1. In the peephole optimization function OptimizeIndividualFunctions, always
remove tail call from objc_autorelease.
2. Whenever we convert to/from an objc_autorelease, set/unset the tail call
keyword as appropriate.
*NOTE* I also handled the case where objc_autorelease is converted in
OptimizeReturns to an autoreleaseRV which still violates the ARC semantics. I
will be removing that in a later patch and I wanted to make sure that the tree
is in a consistent state vis-a-vis ARC always.
Additionally some test cases are provided and all tests that have tail call marked
objc_autorelease keywords have been modified so that tail call has been removed.
*NOTE* One test fails due to a separate bug that I am going to commit soon. Thus
I marked the check line TMP: instead of CHECK: so make check does not fail.
llvm-svn: 172287
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register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 172284
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When tryEvict() is looking for a cheaper register in the allocation
order, skip the tail of too expensive registers when possible.
llvm-svn: 172281
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