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* [MIPS] Fix illegal type assert in single-float modeSimon Atanasyan2018-09-111-3/+8
| | | | | | | | | | | | An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
* [SanitizerCoverage] Create comdat for global arrays.Matt Morehouse2018-09-111-14/+31
| | | | | | | | | | | | | | | | | Summary: Place global arrays in comdat sections with their associated functions. This makes sure they are stripped along with the functions they reference, even on the BFD linker. Reviewers: eugenis Reviewed By: eugenis Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51902 llvm-svn: 341951
* [MemorySSAUpdater] Avoid creating self-referencing MemoryDefsAlexandros Lamprineas2018-09-111-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=38807, which occurred while compiling SemaTemplateInstantiate.cpp with clang and GVNHoist enabled. In the following example: 1=def(entry) / \ 2=def(1) 4=def(1) 3=def(2) 5=def(4) When removing the MemoryDef 2=def(1) from its basic block, and just before adding it to the end of the parent basic block, we first replace all its uses with the defining memory access: 3=def(2) -> 3=def(1) Then we call insertDef for adding 2=def(1) to the parent basic block, where we replace the uses of 1=def(entry) with 2=def(1). Doing so we create a self reference: 2=def(1) -> 2=def(2) (bad) 3=def(1) -> 3=def(2) (ok) 4=def(1) -> 4=def(2) (ok) Differential Revision: https://reviews.llvm.org/D51801 llvm-svn: 341947
* pdb output: Initialize padding in PublicsStreamHeader.Nico Weber2018-09-111-2/+3
| | | | | | | | | Makes the produced pdbs more deterministic; before they'd contain 2 arbitary bytes where this padding was. Also reorder initialization to match the order of the fields in the struct (nfc) llvm-svn: 341945
* [ARM] Add smlald support in ARMParallelDSPSam Parker2018-09-111-13/+41
| | | | | | | | | Search from i64 reducing phis, as well as i32, to allow the generation of smlald instructions. Differential Revision: https://reviews.llvm.org/D51101 llvm-svn: 341941
* [MIPS] ORC JIT supportPetar Jovanovic2018-09-113-2/+491
| | | | | | | | | | | | This patch adds support for ORC JIT for mips/mips64 architecture. In common code $static is changed to __ORCstatic because on MIPS architecture "$" is a reserved character. Patch by Luka Ercegovcevic Differential Revision: https://reviews.llvm.org/D49665 llvm-svn: 341934
* [ARM] Enable ARMCodeGenPrepare by defaultSam Parker2018-09-111-1/+1
| | | | | | | | | We've had the pass enabled downstream for a couple of weeks and it seems to be okay, so enable it by default. Differential Revision: https://reviews.llvm.org/D51920 llvm-svn: 341932
* [AMDGPU] Preliminary patch for divergence driven instruction selection. ↵Alexander Timofeev2018-09-114-21/+62
| | | | | | | | | Immediate selection predicate changed Differential revision: https://reviews.llvm.org/D51734 Reviewers: rampitec llvm-svn: 341928
* [FuncAttrs] Remove "access range attributes" for read-none functionsJohannes Doerfert2018-09-111-0/+7
| | | | | | | | | | The presence of readnone and an access range attribute (argmemonly, inaccessiblememonly, inaccessiblemem_or_argmemonly) is considered an error by the verifier. This seems strict but also not wrong. This patch makes sure function attribute detection will remove all access range attributes for readnone functions. llvm-svn: 341927
* [LoopInfo] Fix Loop::getLoopID() for loops with multiple latchesJohannes Doerfert2018-09-111-12/+5
| | | | | | | | The previous implementation traversed all loop blocks and bailed if one was not a latch block. Since we are only interested in latch blocks, we should only traverse those. llvm-svn: 341926
* [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instructionSimon Atanasyan2018-09-111-0/+3
| | | | | | | | | | | | | | | | | | | | | MIPS ISAs start to support third operand for the `rdhwr` instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code. This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA. Ideally, we also need to reject three-operands version of the `rdhwr` instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch. This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861) Differential revision: https://reviews.llvm.org/D51773 llvm-svn: 341919
* [NFC] Sanitizing asserts for OrderedBasicBlockMax Kazantsev2018-09-111-0/+3
| | | | llvm-svn: 341917
* [X86] In combineMOVMSK, look through int->fp bitcasts before callling ↵Craig Topper2018-09-111-1/+7
| | | | | | | | SimplifyDemandedBits. MOVMSKPS and MOVMSKPD both take FP types, but likely the operations before it are on integer types with just a int->fp bitcast between them. If the bitcast isn't used by anything else and doesn't change the element width we can look through it to simplify the integer ops. llvm-svn: 341915
* [XRay] Ensure lambda outlives llvm::function_refDean Michael Berris2018-09-111-2/+2
| | | | | | Follow-up to D51912. llvm-svn: 341912
* [XRay] Write the TSC along with CPUIDDean Michael Berris2018-09-111-1/+1
| | | | | | | | Fixes builds in non-little-endian systems. This is a follow-up to D51911. llvm-svn: 341909
* [XRay] Use FDR Records+Visitors for Trace LoadingDean Michael Berris2018-09-114-545/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In this change, we overhaul the implementation for loading `llvm::xray::Trace` objects from files by using the combination of specific FDR Record types and visitors breaking up the logic to reconstitute an execution trace from flight-data recorder mode traces. This change allows us to handle out-of-temporal order blocks as written in files, and more consistently recreate an execution trace spanning multiple blocks and threads. To do this, we use the `WallclockRecord` associated with each block to maintain temporal order of blocks, before attempting to recreate an execution trace. The new addition in this change is the `TraceExpander` type which can be thought of as a decompression/decoding routine. This allows us to maintain the state of an execution environment (thread+process) and create `XRayRecord` instances that fit nicely into the `Trace` container. We don't have a specific unit test for the TraceExpander type, since the end-to-end tests for the `llvm-xray convert` tools already cover precisely this codepath. This change completes the refactoring started with D50441. Depends on D51911. Reviewers: mboerger, eizan Subscribers: mgorny, hiraditya, mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D51912 llvm-svn: 341906
* [XRay] Add TSC to NewCPUId RecordsDean Michael Berris2018-09-112-2/+9
| | | | | | | | | | | | | | | Summary: This more correctly reflects the data written by the FDR mode runtime. This is a continuation of the work in D50441. Reviewers: mboerger, eizan Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51911 llvm-svn: 341905
* [NFC] Rename variableMax Kazantsev2018-09-111-2/+2
| | | | llvm-svn: 341901
* NFC: use bit_cast more in AArch64AddressingModesJF Bastien2018-09-111-24/+11
| | | | | | | | The was previously committed as r341749 then reverted as r341750 because bit_cast needed to do its own thing to check is_trivially_copyable on GCC 4.x. This is now done and std;:array should now get accepted. llvm-svn: 341897
* [LICM] Avoid duplicate work during building AliasSetTrackerSerguei Katkov2018-09-111-8/+6
| | | | | | | | | | | | | | | | | | Currently we re-use cached info from sub loops or traverse them to populate AliasSetTracker. But after that we traverse all basic blocks from the current loop. This is redundant work. All what we need is traversing the all basic blocks from the loop except those which are used to get the data from the cache. This should improve compile time only. Reviewers: mkazantsev, reames, kariddi, anna Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51715 llvm-svn: 341896
* AMDGPU: Remove leftovers from configurable address spacesMatt Arsenault2018-09-112-34/+12
| | | | llvm-svn: 341895
* [IndVars][NFC] Refactor to make modifications of Changed transparentMax Kazantsev2018-09-111-44/+47
| | | | | | | | | | | | | | | | | IndVarSimplify's design is somewhat odd in the way how it reports that some transform has made a change. It has a `Changed` field which can be set from within any function, which makes it hard to track whether or not it was set properly after a transform was made. It leads to oversights in setting this flag where needed, see example in PR38855. This patch removes the `Changed` field, turns it into a local and unifies the signatures of all relevant transform functions to return boolean value which designates whether or not this transform has made a change. Differential Revision: https://reviews.llvm.org/D51850 Reviewed By: skatkov llvm-svn: 341893
* [LICM] (re-)simplify code using MemoryLocation API [NFC]Philip Reames2018-09-111-10/+2
| | | | | | I'd made exactly this same change before, but it appears to have been accidentally reverted in another change. (I'm assuming accidental since it was without comment or test case, and in an unrelated change.) llvm-svn: 341892
* llvm-symbolizer: Fix bug related to TUs interfering with symbolizingDavid Blaikie2018-09-111-13/+16
| | | | | | | | | | | With the merge of TUs and CUs into a single container, some code that relied on the CU range having an ordered range of contiguous addresses (for locating a CU at a given offset) broke. But the units from debug_info (currently only CUs, but CUs and TUs in DWARFv5) are in a contiguous sub-range of that container - searching only through that subrange is still valid & so do that. llvm-svn: 341889
* Prevent Constant Folding From Optimizing inrange GEPPeter Collingbourne2018-09-111-9/+2
| | | | | | | | | | | | | | | This patch does the following things: 1. update SymbolicallyEvaluateGEP so that it bails out if it cannot preserve inrange arribute; 2. update llvm/test/Analysis/ConstantFolding/gep.ll to remove UB in it; 3. remove inaccurate comment above ConstantFoldInstOperandsImpl in llvm/lib/Analysis/ConstantFolding.cpp; 4. add a new regression test that makes sure that no optimizations change an inrange GEP in an unexpected way. Patch by Zhaomo Yang! Differential Revision: https://reviews.llvm.org/D51698 llvm-svn: 341888
* [XRay] Add the `llvm-xray fdr-dump` implementationDean Michael Berris2018-09-112-0/+97
| | | | | | | | | | | | | | | | | | | Summary: In this change, we implement a `BlockPrinter` which orders records in a Block that's been indexed by the `BlockIndexer`. This is used in the `llvm-xray fdr-dump` tool which ties together the various types and utilities we've been working on, to allow for inspection of XRay FDR mode traces both with and without verification. This change is the final step of the refactoring of D50441. Reviewers: mboerger, eizan Subscribers: mgorny, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51846 llvm-svn: 341887
* [InstCombine] Partially revert rL341674 due to PR38897.Alina Sbirlea2018-09-101-35/+8
| | | | | | | | | | | | | | | Summary: Revert min/max changes in rL341674 dues to high compile times causing timeouts (PR38897). Checking in to unblock failing builds. Patch available for post-commit review and re-revert once resolved. Working on a smaller reproducer for PR38897. Reviewers: craig.topper, spatel Subscribers: sanjoy, jlebar, llvm-commits Differential Revision: https://reviews.llvm.org/D51897 llvm-svn: 341883
* Add size remarks to MachineFunctionPassJessica Paquette2018-09-101-0/+36
| | | | | | | | | | | | | This adds per-function size remarks to codegen, similar to what we have in the IR layer as of r341588. This only impacts MachineFunctionPasses. This does the same thing, but for `MachineInstr`s instead of just `Instructions`. After this, when a `MachineFunctionPass` modifies the number of `MachineInstr`s in the function it ran on, you'll get a remark. To enable this, use the size-info analysis remark as before. llvm-svn: 341876
* [ORC] Render unresolved symbol addresses as "<not resolved>" in JITDylib::dump.Lang Hames2018-09-101-2/+5
| | | | | | This is easier to spot among the real addresses than "0x0000000000000000". llvm-svn: 341873
* [ORC] Simplify LLJIT::Create by removing the ExecutionSession parameter.Lang Hames2018-09-101-6/+6
| | | | | | | The Create method can just construct the ExecutionSession, rather than having the client pass it in. llvm-svn: 341872
* Re-run clang-format on one file.Zachary Turner2018-09-101-133/+184
| | | | | | | | | clang-format was getting confused due to the presence of a macro invocation that was not terminated by a semicolon. Fixed this by terminating the macro lines with semicolons and re-ran clang-format on the file. llvm-svn: 341864
* [PDB] Change uint32_t to SymIndex wherever it makes sense.Zachary Turner2018-09-107-52/+31
| | | | | | Although it's just a typedef, it helps for readability. NFC. llvm-svn: 341863
* Move FeatureAES from SLM, WSM and SNB to GLM and SKLErich Keane2018-09-101-3/+1
| | | | | | | | | | | | | Complements https://reviews.llvm.org/D51510 and matches https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01940.html GoldmontProc already has FeatureAES. Patch By: thiagomacieira Differential Revision: https://reviews.llvm.org/D51565 llvm-svn: 341861
* [X86] Mark the ISD::SETLT/SETLE condition codes as illegal for v32i16/v64i8 ↵Craig Topper2018-09-101-0/+5
| | | | | | | | to match the other vector types. I'm having a hard time finding a test case for this, but we should be consistent here. The fact that we canonicalize all zeros and all ones constants to vXi32 and all other constants to loads makes this hard to hit the easy DAG combine infinite loop we get for some of the other types. llvm-svn: 341859
* API to update MemorySSA for cloned blocks and added CFG edges.Alina Sbirlea2018-09-102-15/+548
| | | | | | | | | | | | | | | | Summary: End goal is to update MemorySSA in all loop passes. LoopUnswitch clones all blocks in a loop. SimpleLoopUnswitch clones some blocks. LoopRotate clones some instructions. Some of these loop passes also make CFG changes. This is an API based on what I found needed in LoopUnswitch, SimpleLoopUnswitch, LoopRotate, LoopInstSimplify, LoopSimplifyCFG. Adding dependent patches using this API for context. Reviewers: george.burgess.iv, dberlin Subscribers: sanjoy, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D45299 llvm-svn: 341855
* [Hexagon] Split large offsets into properly aligned addendsKrzysztof Parzyszek2018-09-101-0/+9
| | | | llvm-svn: 341851
* [InstCombine] use SelectInst operand names to make code clearer; NFCSanjay Patel2018-09-101-8/+10
| | | | | | Cleanup step for D51433. llvm-svn: 341850
* [ARC] Fix macro usage (DEBUG -> LLVM_DEBUG)Tatyana Krasnukha2018-09-101-1/+1
| | | | llvm-svn: 341844
* [AMDGPU] Preliminary patch for divergence driven instruction selection. ↵Alexander Timofeev2018-09-101-5/+33
| | | | | | | | | | Inline immediate move to V_MADAK_F32. Differential revision: https://reviews.llvm.org/D51586 Reviewer: rampitec llvm-svn: 341843
* [AST] Visit memtransfer arguments in orderPhilip Reames2018-09-101-1/+1
| | | | | | | | | | The only point to this change is the test diffs. When I remove this code entirely (in favor of the recently added generic handling), I don't want there to be any confusion due to spurious test diffs. As an aside, the fact out tests are AST construction order dependent is not great. I thought about fixing that, but the reasonable schemes I might want (e.g. sort by name) need the test diffs anyways. Philip llvm-svn: 341841
* [MIPS GlobalISel] Select icmpPetar Jovanovic2018-09-103-0/+89
| | | | | | | | | | Select 32bit integer compare instructions for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51489 llvm-svn: 341840
* HotColdSplitting: check that target supports cold calling conventionSebastian Pop2018-09-101-4/+13
| | | | | | | | | Before tagging a function with coldcc make sure the target supports cold calling convention. Without this patch HotColdSplitting pass fails on aarch64 with: fatal error: error in backend: Unsupported calling convention. llvm-svn: 341838
* add flag instead of using a constant [NFC]Sebastian Pop2018-09-101-1/+5
| | | | llvm-svn: 341837
* make flag name more specific to gvn [NFC]Sebastian Pop2018-09-101-2/+2
| | | | llvm-svn: 341836
* InstCombine: move hasOneUse check to the top of foldICmpAddConstantTim Northover2018-09-101-3/+3
| | | | | | | | | | | | There were two combines not covered by the check before now, neither of which actually differed from normal in the benefit analysis. The most recent seems to be because it was just added at the top of the function (naturally). The older is from way back in 2008 (r46687) when we just didn't put those checks in so routinely, and has been diligently maintained since. llvm-svn: 341831
* [Sparc] Move SparcTargetStreamer.h to the MC Desc, where the implementation ↵Benjamin Kramer2018-09-102-4/+3
| | | | | | is already llvm-svn: 341826
* [LLD][COFF] Cleanup error messages / add more coverage testsAlexandre Ganea2018-09-101-1/+1
| | | | | | | | | | | | - Log the reason for a PDB or precompiled-OBJ load failure - Properly handle out-of-date PDB or precompiled-OBJ signature by displaying a corresponding error - Slightly change behavior on PDB failure: any subsequent load attempt from another OBJ would result in the same error message being logged - Slightly change behavior on PDB failure: retry with filename only if previous error was ENOENT ("no such file or directory") - Tests: a. for native PDB errors; b. cover all the cases above Differential Revision: https://reviews.llvm.org/D51559 llvm-svn: 341825
* [Target] Untangle disassemblersBenjamin Kramer2018-09-1015-43/+37
| | | | | | | Disassemblers cannot depend on main target headers. The same is true for MCTargetDesc, but there's a lot more cleanup needed for that. llvm-svn: 341822
* Don't create a temporary vector of loop blocks just to iterate over them.Benjamin Kramer2018-09-103-14/+9
| | | | | | Loop's getBlocks returns an ArrayRef. llvm-svn: 341821
* [GVN] Invalidate cached info for values replaced by equality propagationJohn Brawn2018-09-101-0/+6
| | | | | | | | | When GVN propagates an equality by replacing one value with another it also needs to invalidate the cached information for the value being replaced. Differential Revision: https://reviews.llvm.org/D51218 llvm-svn: 341820
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