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* GVN-hoist: fix early exit logicSebastian Pop2016-08-041-4/+11
| | | | | | | | | | The patch splits a complex && if condition into easier to read and understand logic. That wrong early exit condition was letting some instructions with not all operands available pass through when HoistingGeps was true. Differential Revision: https://reviews.llvm.org/D23174 llvm-svn: 277785
* IR: Provide an IRBuilder Inserter that calls a callback after insertionJustin Bogner2016-08-042-25/+10
| | | | | | | | | | Add a generalized IRBuilderCallbackInserter, which is just given a callback to execute after insertion. This can be used to get rid of the custom inserter in InstCombine, which will in turn allow me to add target specific InstCombineCalls API for intrinsics without horrible layering violations. llvm-svn: 277784
* [LV, X86] Be more optimistic about vectorizing shifts.Michael Kuperstein2016-08-044-24/+41
| | | | | | | | | | | | | | | Shifts with a uniform but non-constant count were considered very expensive to vectorize, because the splat of the uniform count and the shift would tend to appear in different blocks. That made the splat invisible to ISel, and we'd scalarize the shift at codegen time. Since r201655, CodeGenPrepare sinks those splats to be next to their use, and we are able to select the appropriate vector shifts. This updates the cost model to to take this into account by making shifts by a uniform cheap again. Differential Revision: https://reviews.llvm.org/D23049 llvm-svn: 277782
* [InstCombine] use m_APInt to allow icmp eq (mul X, C1), C2 folds for splat ↵Sanjay Patel2016-08-041-6/+5
| | | | | | | | | | | | | | | | constant vectors This concludes the splat vector enhancements for foldICmpEqualityWithConstant(). Other commits in this series: https://reviews.llvm.org/rL277762 https://reviews.llvm.org/rL277752 https://reviews.llvm.org/rL277738 https://reviews.llvm.org/rL277731 https://reviews.llvm.org/rL277659 https://reviews.llvm.org/rL277638 https://reviews.llvm.org/rL277629 llvm-svn: 277779
* Clean up the logic of the Archive::Child::Child() with an assert to know Err ↵Kevin Enderby2016-08-041-21/+23
| | | | | | | | | | | | | | | | | is not a nullptr when we are pointed at real data. David Blaikie pointed out some odd logic in the case the Err value was a nullptr and Lang Hames suggested it could be cleaned it up with an assert to know that Err is not a nullptr when we are pointed at real data. As only in the case of constructing the sentinel value by pointing it at null data is Err is permitted to be a nullptr, since no error could occur in that case. With this change the testing for “if (Err)” is removed from the constructor’s logic and *Err is used directly without any check after the assert(). llvm-svn: 277776
* GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.Tim Northover2016-08-042-3/+9
| | | | | | | These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
* GlobalISel: add support for G_MULTim Northover2016-08-041-0/+2
| | | | llvm-svn: 277774
* GlobalISel: implement narrowing for G_ADD.Tim Northover2016-08-043-2/+57
| | | | llvm-svn: 277769
* GVNHoist: Don't hoist convergent callsMatt Arsenault2016-08-041-0/+4
| | | | llvm-svn: 277767
* [ExecutionEngine] Refactor - Roll JITSymbolFlags functionality into JITSymbol.hLang Hames2016-08-044-4/+49
| | | | | | and remove the JITSymbolFlags header. llvm-svn: 277766
* [coroutines] Part 4[ab]: Coroutine Devirtualization: Lower coro.resume and ↵David Majnemer2016-08-045-6/+225
| | | | | | | | | | | | | | | | coro.destroy. This is the forth patch in the coroutine series. CoroEaly pass now lowers coro.resume and coro.destroy intrinsics by replacing them with an indirect call to an address returned by coro.subfn.addr intrinsic. This is done so that CGPassManager recognizes devirtualization when CoroElide replaces a call to coro.subfn.addr with an appropriate function address. Patch by Gor Nishanov! Differential Revision: https://reviews.llvm.org/D22998 llvm-svn: 277765
* [InstCombine] use m_APInt to allow icmp eq (and X, C1), C2 folds for splat ↵Sanjay Patel2016-08-041-14/+9
| | | | | | constant vectors llvm-svn: 277762
* [OpenCL] Add missing tests for getOCLTypeNameYaxun Liu2016-08-041-1/+1
| | | | | | | | | | Adding missing tests for OCL type names for half, float, double, char, short, long, and unknown. Patch by Aaron En Ye Shi. Differential Revision: https://reviews.llvm.org/D22964 llvm-svn: 277759
* [CodeView] Use llvm::Error instead of std::error_code.Zachary Turner2016-08-043-103/+126
| | | | | | | This eliminates the remnants of std::error_code from the DebugInfo libraries. llvm-svn: 277758
* AArch64: don't assume all i128s are BUILD_PAIRsTim Northover2016-08-041-6/+13
| | | | | | | It leads to a crash when they're not. I'm *sure* I've made this mistake before, at least once. llvm-svn: 277755
* [InstCombine] use m_APInt to allow icmp eq (or X, C1), C2 folds for splat ↵Sanjay Patel2016-08-041-9/+7
| | | | | | constant vectors llvm-svn: 277752
* GlobalISel: also add G_TRUNC to IRTranslator.Tim Northover2016-08-041-1/+3
| | | | llvm-svn: 277749
* GlobalISel: add code to widen scalar G_ADDTim Northover2016-08-043-1/+39
| | | | llvm-svn: 277747
* [WebAssembly] Check return value of getRegForValue in FastISelDerek Schuff2016-08-041-0/+13
| | | | | | | | | | | | Previously, FastISel for WebAssembly wasn't checking the return value of `getRegForValue` in certain cases, which would generate instructions referencing NoReg. This patch fixes this behavior. Patch by Dominic Chen Differential Revision: https://reviews.llvm.org/D23100 llvm-svn: 277742
* [Hexagon] Validate register class when doing bit simplificationKrzysztof Parzyszek2016-08-041-10/+33
| | | | llvm-svn: 277740
* [InstCombine] use m_APInt to allow icmp eq (op X, Y), C folds for splat ↵Sanjay Patel2016-08-042-18/+6
| | | | | | | | | constant vectors I'm removing a misplaced pair of more specific folds from InstCombine in this patch as well, so we know where those folds are happening in InstSimplify. llvm-svn: 277738
* [X86][SSE] Rename target shuffle unary permute matching function. NFCI.Simon Pilgrim2016-08-041-6/+6
| | | | | | In preparation for adding a binary permute matching function. llvm-svn: 277737
* LoadStoreVectorizer: Remove TargetBaseAlign. Keep alignment for stack ↵Alina Sbirlea2016-08-043-14/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | adjustments. Summary: TargetBaseAlign is no longer required since LSV checks if target allows misaligned accesses. A constant defining a base alignment is still needed for stack accesses where alignment can be adjusted. Previous patch (D22936) was reverted because tests were failing. This patch also fixes the cause of those failures: - x86 failing tests either did not have the right target, or the right alignment. - NVPTX failing tests did not have the right alignment. - AMDGPU failing test (merge-stores) should allow vectorization with the given alignment but the target info considers <3xi32> a non-standard type and gives up early. This patch removes the condition and only checks for a maximum size allowed and relies on the next condition checking for %4 for correctness. This should be revisited to include 3xi32 as a MVT type (on arsenm's non-immediate todo list). Note that checking the sizeInBits for a MVT is undefined (leads to an assertion failure), so we need to create an EVT, hence the interface change in allowsMisaligned to include the Context. Reviewers: arsenm, jlebar, tstellarAMD Subscribers: jholewinski, arsenm, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D23068 llvm-svn: 277735
* [mips] Set Personality and LSDA encoding for FreeBSDDaniel Sanders2016-08-041-0/+8
| | | | | | | | | | Reviewers: seanbruno, sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits, seanbruno Differential Revision: https://reviews.llvm.org/D23113 llvm-svn: 277732
* [InstCombine] use m_APInt to allow icmp eq (sub C1, X), C2 folds for splat ↵Sanjay Patel2016-08-041-4/+4
| | | | | | constant vectors llvm-svn: 277731
* [X86][SSE] Split off shuffle mask canonicalization from lowerVectorShuffle. ↵Simon Pilgrim2016-08-041-52/+67
| | | | | | | | | | NFCI. The new function now returns true if the shuffle should be commuted. This will allow target shuffle combines to share the code. llvm-svn: 277728
* [Hexagon] Clear kill flags from modified registers in peephole optimizerKrzysztof Parzyszek2016-08-041-1/+4
| | | | llvm-svn: 277727
* [X86] Heuristic to selectively build Newton-Raphson SQRT estimationNikolai Bozhenov2016-08-049-7/+54
| | | | | | | | | | | | | | | | | | | | | On modern Intel processors hardware SQRT in many cases is faster than RSQRT followed by Newton-Raphson refinement. The patch introduces a simple heuristic to choose between hardware SQRT instruction and Newton-Raphson software estimation. The patch treats scalars and vectors differently. The heuristic is that for scalars the compiler should optimize for latency while for vectors it should optimize for throughput. It is based on the assumption that throughput bound code is likely to be vectorized. Basically, the patch disables scalar NR for big cores and disables NR completely for Skylake. Firstly, scalar SQRT has shorter latency than NR code in big cores. Secondly, vector SQRT has been greatly improved in Skylake and has better throughput compared to NR. Differential Revision: https://reviews.llvm.org/D21379 llvm-svn: 277725
* [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructionsHrvoje Varga2016-08-045-7/+35
| | | | | | Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
* [X86][SSE] Add initial costs for vector CTTZ/CTLZSimon Pilgrim2016-08-041-4/+41
| | | | llvm-svn: 277716
* [X86][SSE] Don't decide when to scalarize CTTZ/CTLZ for performance at ↵Simon Pilgrim2016-08-041-12/+4
| | | | | | | | lowering - this is what cost models are for Improved CTTZ/CTLZ costings will be added shortly llvm-svn: 277713
* [mips] Enable tail calls by defaultSimon Dardis2016-08-048-10/+61
| | | | | | | | | | | | | | | | | | Enable tail calls by default for (micro)MIPS(64). microMIPS is slightly more tricky than doing it for MIPS(R6) or microMIPSR6. microMIPS has two instruction encodings: 16bit and 32bit along with some restrictions on the size of the instruction that can fill the delay slot. For safe tail calls for microMIPS, the delay slot filler attempts to find a correct size instruction for the delay slot of TAILCALL pseudos. Reviewers: dsanders, vkalintris Subscribers: jfb, dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D21138 llvm-svn: 277708
* Typo fix in comment. NFCDiana Picus2016-08-041-1/+1
| | | | llvm-svn: 277704
* [XRay] Align entry and return sleds to 2 byte boundariesDean Michael Berris2016-08-041-2/+4
| | | | | | | | | | | | | | | | | | | | This should ensure that we can atomically write two bytes (on top of the retq and the one past it) and have those two bytes not straddle cache lines. We also move the label past the alignment instruction so that we can refer to the actual first instruction, as opposed to potential padding before the aligned instruction. Update the tests to allow us to reflect the new order of assembly. Reviewers: rSerge, echristo, majnemer Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23101 llvm-svn: 277701
* Add popcount(n) == bitsize(n) -> n == -1 transformation.Amaury Sechet2016-08-041-4/+10
| | | | | | | | | | | | Summary: As per title. Reviewers: majnemer, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23139 llvm-svn: 277694
* Forgot the dyn_cast_or_null intended for r277691.David Majnemer2016-08-041-1/+1
| | | | llvm-svn: 277693
* Reinstate "[CloneFunction] Don't remove side effecting calls"David Majnemer2016-08-042-4/+37
| | | | | | | This reinstates r277611 + r277614 and reverts r277642. A cast_or_null should have been a dyn_cast_or_null. llvm-svn: 277691
* Revert "GVN-hoist: enable by default" & "Make GVN Hoisting obey optnone/bisect."Bruno Cardoso Lopes2016-08-041-2/+2
| | | | | | | | This reverts commits r277685 & r277688. r277685 broke compiler-rt compilation http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/23335 and r277685 is a followup from it. llvm-svn: 277690
* [PM] Change the name of the repeating utility to something lessChandler Carruth2016-08-041-4/+4
| | | | | | | | | | | overloaded (and simpler). Sean rightly pointed out in code review that we've started using "wrapper pass" as a specific part of the old pass manager, and in fact it is more applicable there. Here, we really have a pass *template* to build a repeated pass, so call it that. llvm-svn: 277689
* GVN-hoist: enable by defaultSebastian Pop2016-08-041-2/+2
| | | | | | | | | | As we addressed all compilation time problems with GVN-hoist https://llvm.org/bugs/show_bug.cgi?id=28670 this patch turns GVN-hoist back by default. Differential Revision: https://reviews.llvm.org/D23136 llvm-svn: 277685
* pdbdump: Fix crash bug.Rui Ueyama2016-08-031-1/+4
| | | | | | | | | | pdbdump calls DbiStreamBuilder::commit through PDBFileBuilder::commit without calling DbiStreamBuilder::finalize. Because `finalize` initializes `Header` member, `Header` remained nullptr which caused a crash bug. Differential Revision: https://reviews.llvm.org/D23143 llvm-svn: 277681
* RenameIndependentSubregs: Fix liveness query in rewriteOperands()Matthias Braun2016-08-031-7/+6
| | | | | | | | rewriteOperands() always performed liveness queries at the base index rather than the RegSlot/Base as apropriate for the machine operand. This could lead to illegal rewriting in some cases. llvm-svn: 277661
* [InstCombine] use m_APInt to allow icmp eq (add X, C1), C2 folds for splat ↵Sanjay Patel2016-08-031-6/+8
| | | | | | constant vectors llvm-svn: 277659
* Clean up of libObject/Archive interfaces and change the last three uses of ↵Kevin Enderby2016-08-031-40/+75
| | | | | | | | | | | | ErrorOr<> changing them to Expected<> to allow them to pass through llvm Errors. No functional change. This commit by itself will break the next lld builds.  I’ll be committing the matching change for lld immediately next. llvm-svn: 277656
* [PPC] Handling CallInst in PPCBoolRetToIntGuozhi Wei2016-08-031-7/+13
| | | | | | | | This patch fixes pr25548. Current implementation of PPCBoolRetToInt doesn't handle CallInst correctly, so it failed to do the intended optimization when there is a CallInst with parameters. This patch fixed that. llvm-svn: 277655
* Revert "[ARM] Constant Materialize: imms with specific value can be encoded ↵Bruno Cardoso Lopes2016-08-031-3/+1
| | | | | | | | | | | into mov.w" This reverts commit r277610 / d619aa8878c3dafcc0d29a46517f63ff3209fdd4. This make subtarget-no-movt.ll fail in http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_check/26892, llvm-svn: 277654
* [MSSA] Fix a bug in MemorySSA's move ctor.George Burgess IV2016-08-031-0/+2
| | | | | | | Not a correctness issue, but it would be nice if we didn't have to recompute our block numbering (worst-case) every time we move MSSA. llvm-svn: 277652
* GVN-hoist: limit the length of dependent instructionsSebastian Pop2016-08-031-0/+10
| | | | | | | | | | Limit the number of times the while(1) loop is executed. With this restriction the number of hoisted instructions does not change in a significant way on the test-suite. Differential Revision: https://reviews.llvm.org/D23028 llvm-svn: 277651
* GVN-hoist: compute DFS numbers onceSebastian Pop2016-08-031-12/+22
| | | | | | | | | With this patch we compute the DFS numbers of instructions only once and update them during the code generation when an instruction gets hoisted. Differential Revision: https://reviews.llvm.org/D23021 llvm-svn: 277650
* GVN-hoist: compute MSSA once per function (PR28670)Sebastian Pop2016-08-031-12/+49
| | | | | | | | With this patch we compute the MemorySSA once and update it in the code generator. Differential Revision: https://reviews.llvm.org/D22966 llvm-svn: 277649
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