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* AMDGPU: Add StackPtr and FramePtr registers to MFIMatt Arsenault2017-04-242-0/+26
| | | | | | These will be necessary for setting up call sequences. llvm-svn: 301208
* AMDGPU: Move trap lowering to DAGMatt Arsenault2017-04-245-59/+66
| | | | | | | | | | | Fixes traps in any block besides the entry block, and fixes depending on a live-in physical register by using a virtual register copy. Also happens to stop emitting a nop in the case debug trap is not supported. llvm-svn: 301206
* [DomPrinter] Add a way to programmatically dump a dot representation.Davide Italiano2017-04-241-0/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D32145 llvm-svn: 301205
* [llvm-pdbdump] Re-write the record layout code to be more resilient.Zachary Turner2017-04-244-203/+168
| | | | | | | | This reworks the way virtual bases are handled, and also the way padding is detected across multiple levels of aggregates, producing a much more accurate result. llvm-svn: 301203
* [APInt] Simplify the zext and sext methodsCraig Topper2017-04-241-33/+18
| | | | | | | | | | This replaces a hand written copy loop with a call to memcpy for both zext and sext. For sext, it replaces multiple if/else blocks propagating sign information forward. Now we just do a copy, a sign extension on the last copied word, a memset, and clearUnusedBits. Differential Revision: https://reviews.llvm.org/D32417 llvm-svn: 301201
* InstCombine: Fix assert when reassociating fsub with undefMatt Arsenault2017-04-241-0/+5
| | | | | | | | | | | | | There is logic to track the expected number of instructions produced. It thought in this case an instruction would be necessary to negate the result, but here it folded into a ConstantExpr fneg when the non-undef value operand was cancelled out by the second fsub. I'm not sure why we don't fold constant FP ops with undef currently, but I think that would also avoid this problem. llvm-svn: 301199
* [APInt] Add ashrInPlace method and rewrite ashr to make a copy and then call ↵Craig Topper2017-04-241-76/+36
| | | | | | | | | | | | ashrInPlace. This patch adds an in place version of ashr to match lshr and shl which were recently added. I've tried to make this similar to the lshr code with additions to handle the sign extension. I've also tried to do this with less if checks than the current ashr code by sign extending the original result to a word boundary before doing any of the shifting. This removes a lot of the complexity of determining where to fill in sign bits after the shifting. Differential Revision: https://reviews.llvm.org/D32415 llvm-svn: 301198
* AMDGPU: Move v_readlane lane select from VGPR to SGPRNicolai Haehnle2017-04-241-0/+13
| | | | | | | | | | | | | | | | | Summary: Fix a compiler bug when the lane select happens to end up in a VGPR. Clarify the semantic of the corresponding intrinsic to be that of the corresponding GLSL: the lane select must be uniform across a wave front, otherwise results are undefined. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D32343 llvm-svn: 301197
* Compute safety information in a much finer granularity.Xin Tong2017-04-243-38/+20
| | | | | | | | | | | | | | | | | | | Summary: Instead of keeping a variable indicating whether there are early exits in the loop. We keep all the early exits. This improves LICM's ability to move instructions out of the loop based on is-guaranteed-to-execute. I am going to update compilation time as well soon. Reviewers: hfinkel, sanjoy, efriedma, mkuper Reviewed By: hfinkel Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D32433 llvm-svn: 301196
* InstCombine/AMDGPU: Fix constant folding of llvm.amdgcn.{icmp,fcmp}Nicolai Haehnle2017-04-241-2/+20
| | | | | | | | | | | | | | | | | | Summary: The return value of these intrinsics should always have 0 bits for inactive threads. This means that when all arguments are constant and the comparison evaluates to true, the intrinsic should return the current exec mask. Fixes some GL_ARB_shader_ballot tests. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D32344 llvm-svn: 301195
* [GlobalISel][X86] Lower FormalArgument/Ret using ↵Igor Breger2017-04-242-22/+11
| | | | | | | | | | | | | | | | G_MERGE_VALUES/G_UNMERGE_VALUES. Summary: [GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES. Reviewers: zvi, t.p.northover, guyblank Reviewed By: t.p.northover Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32288 llvm-svn: 301194
* [DAGCombiner] Updated bswap byte offset variable names to be more ↵Simon Pilgrim2017-04-241-13/+15
| | | | | | | | descriptive. NFC As discussed on D32039, use MaskByteOffset to describe the variable and also pull out repeated getOpcode() calls. llvm-svn: 301193
* [APInt] Fix repeated word in comments. NFCCraig Topper2017-04-241-2/+2
| | | | llvm-svn: 301192
* AMDGPU: Fix crash when scheduling non-memory SMRD instructionsNicolai Haehnle2017-04-241-0/+5
| | | | | | | | | | | | Summary: Fixes piglit spec/arb_shader_clock/execution/* Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D32345 llvm-svn: 301191
* [SDAG] Teach Chain Analysis about BaseIndexOffset addressing.Nirav Dave2017-04-241-2/+13
| | | | | | | | | | | | | | | | | | While we use BaseIndexOffset in FindBetterNeighborChains to appropriately realize they're almost the same address and should be improved concurrently we do not use it in isAlias using the non-index understanding FindBaseOffset instead. Adding a BaseIndexOffset check in isAlias like should allow indexed stores to be merged. FindBaseOffset to be excised in subsequent patch. Reviewers: jyknight, aditya_nandakumar, bogner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31987 llvm-svn: 301187
* [SystemZ] Update kill-flag in splitMove().Jonas Paulsson2017-04-241-2/+3
| | | | | | | EarlierMI needs to clear the kill flag on the first operand in case of a store. Review: Ulrich Weigand llvm-svn: 301177
* Add SUSE vendorIsmail Donmez2017-04-241-0/+2
| | | | | | | | | | | | | | Summary: SUSE's ARM triples end with -gnueabi even though they are hard-float. This requires special handling of SUSE ARM triples. Hence we need a way to differentiate the SUSE as vendor. This CL adds that. Reviewers: chandlerc, compnerd, echristo, rengolin Reviewed By: rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D32426 llvm-svn: 301174
* [DWARF] - Take relocations in account when extracting ranges from .debug_rangesGeorge Rimar2017-04-243-14/+22
| | | | | | | | | | | | | | | I found this when investigated "Bug 32319 - .gdb_index is broken/incomplete" for LLD. When we have object file with .debug_ranges section it may be filled with zeroes. Relocations are exist in file to relocate this zeroes into real values later, but until that a pair of zeroes is treated as terminator. And DWARF parser thinks there is no ranges at all when I am trying to collect address ranges for building .gdb_index. Solution implemented in this patch is to take relocations in account when parsing ranges. Differential revision: https://reviews.llvm.org/D32228 llvm-svn: 301170
* [ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIVDiana Picus2017-04-242-0/+55
| | | | | | | | | | | | | | We have to widen the operands to 32 bits and then we can either use hardware division if it is available or lower to a libcall otherwise. At the moment it is not enough to set the Legalizer action to WidenScalar, since for libcalls it won't know what to do (it won't be able to find what size to widen to, because it will find Libcall and not Legal for 32 bits). To hack around this limitation, we request Custom lowering, and as part of that we widen first and then we run another legalizeInstrStep on the widened DIV. llvm-svn: 301166
* [Arch64AsmParser] better diagnostic for isbSjoerd Meijer2017-04-241-7/+5
| | | | | | | | | | | Instruction isb takes as an operand either 'sy' or an immediate value. This improves the diagnostic when the string is not 'sy' and adds a test case for this which was missing. This also adds tests to check invalid inputs for dsb and dmb. Differential Revision: https://reviews.llvm.org/D32227 llvm-svn: 301165
* [ARM] GlobalISel: Support G_(S|U)DIV for s32Diana Picus2017-04-243-0/+19
| | | | | | | | | Add support for both targets with hardware division and without. For hardware division we have to add support throughout the pipeline (legalizer, reg bank select, instruction select). For targets without hardware division, we only need to mark it as a libcall. llvm-svn: 301164
* [GlobalISel] Legalize G_(S|U)DIV libcallsDiana Picus2017-04-241-12/+30
| | | | | | | | | | Treat them the same as the other binary operations that we have so far, but on integers rather than floating point types. Extract the common code into a helper. This will be used in the ARM backend. llvm-svn: 301163
* [ARM] GlobalISel: Select G_CONSTANT with CImm operandsDiana Picus2017-04-241-0/+12
| | | | | | | | | | | | | | When selecting a G_CONSTANT to a MOVi, we need the value to be an Imm operand. We used to just leave the G_CONSTANT operand unchanged, which works in some cases (such as the GEP offsets that we create when referring to stack slots). However, in many other places the G_CONSTANTs are created with CImm operands. This patch makes sure to handle those as well, and to error out gracefully if in the end we don't end up with an Imm operand. Thanks to Oliver Stannard for reporting this issue. llvm-svn: 301162
* [APInt] Make behavior of ashr by BitWidth consistent between single and ↵Craig Topper2017-04-241-1/+3
| | | | | | | | multi word. Previously single word would always return 0 regardless of the original sign. Multi word would return all 0s or all 1s based on the original sign. Now single word takes into account the sign as well. llvm-svn: 301159
* Revert "Refactor DynamicLibrary so searching for a symbol will have a ↵Frederich Munch2017-04-245-359/+275
| | | | | | | | | | defined order.” The changes are causing the i686-mingw32 build to fail. This reverts commit r301153, and the changes for a separate warning on i686-mingw32 in r301155 and r301156. llvm-svn: 301157
* Fix warning converting from boolean to pointer introduced in r301153.Frederich Munch2017-04-242-2/+2
| | | | | | This reverts commit r301155, which was incorrect. llvm-svn: 301156
* Fix warning converting from void* to boolean introduced in r301153.Frederich Munch2017-04-241-1/+1
| | | | llvm-svn: 301155
* Revert "[SCEV] Enable SCEV verification by default in EXPENSIVE_CHECKS builds"Sanjoy Das2017-04-241-10/+3
| | | | | | | This reverts commit r301150. It breaks CodeGen/Hexagon/hwloop-wrap2.ll, reverting while I investigate. llvm-svn: 301154
* Refactor DynamicLibrary so searching for a symbol will have a defined order andFrederich Munch2017-04-245-275/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | libraries are properly unloaded when llvm_shutdown is called. Summary: This was mostly affecting usage of the JIT, where storing the library handles in a set made iteration unordered/undefined. This lead to disagreement between the JIT and native code as to what the address and implementation of particularly on Windows with stdlib functions: JIT: putenv_s("TEST", "VALUE") // called msvcrt.dll, putenv_s JIT: getenv("TEST") -> "VALUE" // called msvcrt.dll, getenv Native: getenv("TEST") -> NULL // called ucrt.dll, getenv Also fixed is the issue of DynamicLibrary::getPermanentLibrary(0,0) on Windows not giving priority to the process' symbols as it did on Unix. Reviewers: chapuni, v.g.vassilev, lhames Reviewed By: lhames Subscribers: danalbert, srhines, mgorny, vsk, llvm-commits Differential Revision: https://reviews.llvm.org/D30107 llvm-svn: 301153
* Fix unused variables / fields warnings in release buildsSanjoy Das2017-04-241-0/+6
| | | | llvm-svn: 301151
* [SCEV] Enable SCEV verification by default in EXPENSIVE_CHECKS buildsSanjoy Das2017-04-241-3/+10
| | | | llvm-svn: 301150
* [SCEV] Fix exponential time complexity by cachingSanjoy Das2017-04-241-19/+63
| | | | llvm-svn: 301149
* [PartialInine]: add triaging optionsXinliang David Li2017-04-231-0/+24
| | | | | | | There are more bugs (runtime failures) triggered when partial inlining is turned on. Add options to help triaging problems. llvm-svn: 301148
* [SCEV] Move towards a verifier without false positivesSanjoy Das2017-04-231-68/+59
| | | | | | | | | | | | | | | This change reboots SCEV's current (off by default) verification logic to avoid false failures. Instead of stringifying trip counts, it maps old and new trip counts to the same ScalarEvolution "universe" and asks ScalarEvolution to compute the difference between them. If the difference comes out to be a non-zero constant, then (barring some corner cases) we *know* we messed up. I've not yet enabled this by default since it hits an exponential time issue in SCEV, but once I fix that, I'll flip it on by default in EXPENSIVE_CHECKS builds. llvm-svn: 301146
* [InstCombine] add/move folds for [not]-xorSanjay Patel2017-04-231-38/+67
| | | | | | | | | | | | We handled all of the commuted variants for plain xor already, although they were scattered around and sometimes folded less efficiently using distributive laws. We had no folds for not-xor. Handling all of these patterns consistently is part of trying to reinstate: https://reviews.llvm.org/rL300977 llvm-svn: 301144
* [PartialInlining] Add optimization remark supportXinliang David Li2017-04-231-4/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D32387 llvm-svn: 301143
* [X86][SSE] Add scheduler class support for SSE42 (PCMPGT) instructionsSimon Pilgrim2017-04-231-6/+10
| | | | llvm-svn: 301142
* [JumpThread] We want to fold (not thread) when all predecessor go to single ↵Xin Tong2017-04-231-0/+30
| | | | | | | | | | | | | | | | | | | | | BB's successor. Summary: In case all predecessor go to a single successor of current BB. We want to fold (not thread). I failed to update the phi nodes properly in the last patch https://reviews.llvm.org/rL300657. Phi nodes values are per predecessor in LLVM. Reviewers: sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32400 llvm-svn: 301139
* Correct grammar. NFCXin Tong2017-04-231-1/+1
| | | | llvm-svn: 301135
* [APInt] In sext single word case, use SignExtend64 and let the APInt ↵Craig Topper2017-04-231-5/+2
| | | | | | | | constructor mask off any excess bits. The current code is trying to be clever with shifts to avoid needing to clear unused bits. But it looks like the compiler is unable to optimize out the unused bit handling in the APInt constructor. Given this its better to just use SignExtend64 and have more readable code. llvm-svn: 301133
* [InstCombine] add pattern matches for commuted variants of xor-to-xorSanjay Patel2017-04-231-34/+55
| | | | | | | | | There's probably some better way to write this that eliminates the code duplication without hurting readability, but at least this eliminates the logic holes and is hopefully slightly more efficient than creating new instructions. llvm-svn: 301129
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate ↵Renato Golin2017-04-2313-34/+37
| | | | | | | | | | | | | | | | within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. llvm-svn: 301111
* Revert "[APInt] Add ashrInPlace method and implement ashr using it. Also fix ↵Renato Golin2017-04-231-26/+73
| | | | | | | | | | a bug in the shift by BitWidth handling." This reverts commit r301094, as it broke all ARM self-hosting bots. PR32754. llvm-svn: 301110
* [X86][MPX] Add load & store instructions of bnd values to ↵Ayman Musa2017-04-231-22/+30
| | | | | | | | | | getLoadStoreRegOpcode function. This is needed for a follow up patch that generates the memory folding tables. Differential Revision: https://reviews.llvm.org/D32232 llvm-svn: 301109
* [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefsArtyom Skrobov2017-04-231-0/+12
| | | | | | | | | | | | | | | | | Summary: D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units. Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC. Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin Reviewed By: javed.absar Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D31081 llvm-svn: 301106
* [APInt] Fix a few places that use APInt::getRawData to operate within the ↵Craig Topper2017-04-233-8/+5
| | | | | | | | | | normal API. getRawData exposes the internal type of the APInt class directly to its users. Ideally we wouldn't expose such an implementation detail. This patch fixes a few of the easy cases by using truncate, extract, or a rotate. llvm-svn: 301105
* [APInt] Use operator<<= where possible. NFCCraig Topper2017-04-233-5/+5
| | | | llvm-svn: 301104
* [APInt] Use operator<<= instead of shl where possible. NFCCraig Topper2017-04-238-20/+20
| | | | llvm-svn: 301103
* [ThinLTO/Summary] Rename anonymous globals as last action ...Davide Italiano2017-04-231-3/+6
| | | | | | | | | | | | | | ... in the per-TU -O0 pipeline. The problem is that there could be passes registered using `addExtensionsToPM()` introducing unnamed globals. Asan is an example, but there may be others. Building cppcheck with `-flto=thin` and `-fsanitize=address` triggers an assertion while we're reading bitcode (in lib/LTO), as the BitcodeReader assumes there are no unnamed globals (because the namer has run). Unfortunately I wasn't able to find an easy way to test this. I added a comment in the hope nobody moves this again. llvm-svn: 301102
* [APInt] Use ashInPlace where possible.Craig Topper2017-04-233-4/+4
| | | | llvm-svn: 301101
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