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* Add a "debugger tuning" concept that allows us to fine-tune how wePaul Robinson2015-07-152-10/+71
| | | | | | | | | | | emit debug info, according to the preferences of the different debuggers used on various targets. Darwin and FreeBSD default to tuning for LLDB; PS4 defaults to tuning for the SCE (Sony Computer Entertainment) debugger. All others default to GDB. Differential Revision: http://reviews.llvm.org/D8506 llvm-svn: 242338
* Fix mergefunc infinite loopJF Bastien2015-07-151-2/+6
| | | | | | | | | | | | | | | Self-referential constants containing references to a merged function no longer cause the MergeFunctions pass to infinite loop. Also adds a reproduction IR which would otherwise fail, which was isolated from a similar issue in Chromium. Author: jrkoenig Reviewers: nlewycky, jfb Subscribers: llvm-commits, nlewycky, jfb Differential Revision: http://reviews.llvm.org/D11208 llvm-svn: 242337
* Simplify a few uses of remove_filename by using parent_path instead.Rafael Espindola2015-07-152-5/+3
| | | | llvm-svn: 242334
* Handle the error of trying to convert a regular archive to a thin one.Rafael Espindola2015-07-151-0/+3
| | | | | | While at it, test that we can add to a thin archive. llvm-svn: 242330
* Rename doFunction() in BFI to calculate() and change its parameters from ↵Cong Hou2015-07-152-2/+2
| | | | | | | | pointers to references. http://reviews.llvm.org/D11196 llvm-svn: 242322
* Analyze recursive PHI nodes in BasicAATobias Edler von Koch2015-07-151-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch allows phi nodes like %x = phi [ %incptr, ... ] [ %var, ... ] %incptr = getelementptr %x, 1 to be analyzed by BasicAliasAnalysis. In aliasPHI, we can detect incoming values that are recursive GEPs with a constant offset. Instead of trying to analyze a recursive GEP (and failing), we now ignore it and instead set the size of the memory referenced by the PHINode to UnknownSize. This represents all the possible memory locations the pointer represented by the PHINode could be advanced to by the GEP. For now, this new behavior is turned off by default to allow debugging of performance degradations seen with SPEC/x86 and Hexagon benchmarks. The flag -basicaa-recphi turns it on. Reviewers: hfinkel, sanjoy Subscribers: tobiasvk_caf, sanjoy, llvm-commits Differential Revision: http://reviews.llvm.org/D10368 llvm-svn: 242320
* Revert "Refactor optimizeUncoalescable logic"Bruno Cardoso Lopes2015-07-151-246/+127
| | | | | | | | | | Likely broke compilation on ARM: http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/13054 This reverts commit 0b7824464fbe3d3f386e2d4aef6a431422709e53. llvm-svn: 242311
* Revert "Look through PHIs to find additional register sources"Bruno Cardoso Lopes2015-07-152-267/+83
| | | | | | | | | | Likely broke compilation on ARM: http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/13054 This reverts commit 131ce4a838c081516cbfed039fc986b33e3979d6. llvm-svn: 242310
* Test commit.Cong Hou2015-07-151-1/+0
| | | | | | This is a test commit (one blank line deleted). llvm-svn: 242308
* Debug Info: Add basic support for external types references.Adrian Prantl2015-07-155-3/+40
| | | | | | | | | | | | | | This is a necessary prerequisite for bootstrapping the emission of debug info inside modules. - Adds a FlagExternalTypeRef to DICompositeType. External types must have a unique identifier. - External type references are emitted using a forward declaration with a DW_AT_signature([DW_FORM_ref_sig8]) based on the UID. http://reviews.llvm.org/D9612 llvm-svn: 242302
* Add missing load/store flags to thumb2 instructions.Pete Cooper2015-07-151-1/+4
| | | | | | | | | | | | | These were the cause of a verifier error when building 7zip with -verify-machineinstrs. Running 'make check' with the verifier triggered the same error on the test here so i've updated the test to run the verifier on one of its runs instead of adding a new one. While looking at this code, there was a stale comment that these instructions were only used for disassembly. This probably used to be the case, but they are now used in the 'ARM load / store optimization pass' too. llvm-svn: 242300
* [PPC64LE] Fix vec_sld semantics for little endianBill Schmidt2015-07-151-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vec_sld interface provides access to the vsldoi instruction. Unlike most of the vec_* interfaces, we do not attempt to change the generated code for vec_sld based on the endian mode. It is too difficult to correctly infer the desired semantics because of different element types, and the corrected instruction sequence is expensive, involving loading a permute control vector and performing a generalized permute. For GCC, this was implemented as "Don't touch the vec_sld" implementation. When it came time for the LLVM implementation, I did the same thing. However, this was hasty and incorrect. In LLVM's version of altivec.h, vec_sld was previously defined in terms of the vec_perm interface. Because vec_perm semantics are adjusted for little endian, this means that leaving vec_sld untouched causes it to generate something different for LE than for BE. Not good. This back-end patch accompanies the changes to altivec.h that change vec_sld's behavior for little endian. Those changes mean that we see slightly different code in the back end when trying to recognize a VSLDOI instruction in isVSLDOIShuffleMask. In particular, a ShuffleKind of 1 (where the two inputs are identical) must now be treated the same way as a ShuffleKind of 2 (little endian with different inputs) when little endian mode is in force. This is because ShuffleKind of 1 is defined using big-endian numbering. This has a ripple effect on LowerBUILD_VECTOR, where we create our own internal VSLDOI instructions. Because these are a ShuffleKind of 1, they will now have their shift amounts subtracted from 16 when recognizing the shuffle mask. To avoid problems we have to subtract them from 16 again before creating the VSLDOI instructions. There are a couple of other uses of BuildVSLDOI, but these do not need to be modified because the shift amount is 8, which is unchanged when subtracted from 16. llvm-svn: 242296
* Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-07-152-83/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 242295
* Refactor optimizeUncoalescable logicBruno Cardoso Lopes2015-07-151-127/+246
| | | | | | | | | | | | | | | - Create a new CopyRewriter for Uncoalescable copy-like instructions - Change the ValueTracker to return a ValueTrackerResult This makes optimizeUncoalescable looks more like optimizeCoalescable and use the CopyRewritter infrastructure. This is also the preparation for looking up into PHI nodes in the ValueTracker. Differential Revision: http://reviews.llvm.org/D11195 llvm-svn: 242294
* [PPC] Disassemble little endian ppc instructions in the right byte orderBenjamin Kramer2015-07-151-8/+17
| | | | | | PR24122. The test is simply a byte swapped version of ppc64-encoding.txt. llvm-svn: 242288
* -Added API for retrieving the default FPU of a CPU from TargetParser.Alexandros Lamprineas2015-07-151-84/+95
| | | | | | | | -Implemented as a table lookup. Change-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018 Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242284
* [PM/AA] Fix *numerous* serious bugs in GlobalsModRef found byChandler Carruth2015-07-151-22/+31
| | | | | | | | | | | | | | | | | | | | | | | | | inspection. While we want to handle calls specially in this code because they should have been modeled by the call graph analysis that precedes it, we should *not* be re-implementing the predicates for whether an instruction reads or writes memory. Those are well defined already. Notably, at least the following issues seem to be clearly missed before: - Ordered atomic loads can "write" to memory by causing writes from other threads to become visible. Similarly for ordered atomic stores. - AtomicRMW instructions quite obviously both read and write to memory. - AtomicCmpXchg instructions also read and write to memory. - Fences read and write to memory. - Invokes of intrinsics or memory allocation functions. I don't have any test cases, and I suspect this has never really come up in the real world. But there is no reason why it wouldn't, and it makes the code simpler to do this the right way. While here, I've tried to make the loops significantly simpler as well and added helpful comments as to what is going on. llvm-svn: 242281
* [SDAG] Optimize unordered comparison in soft-float mode (patch by Anton ↵Alexey Bataev2015-07-151-23/+31
| | | | | | | | | | | Nadolskiy) Current implementation handles unordered comparison poorly in soft-float mode. Consider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0). Such replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero. Differential Revision: http://reviews.llvm.org/D10804 llvm-svn: 242280
* [PowerPC] Use the MachineCombiner to reassociate fadd/fmulHal Finkel2015-07-153-0/+303
| | | | | | | | | | | | | This is a direct port of the code from the X86 backend (r239486/r240361), which uses the MachineCombiner to reassociate (floating-point) adds/muls to increase ILP, to the PowerPC backend. The rationale is the same. There is a lot of copy-and-paste here between the X86 code and the PowerPC code, and we should extract at least some of this into CodeGen somewhere. However, I don't want to do that until this code is enhanced to handle FMAs as well. After that, we'll be in a better position to extract the common parts. llvm-svn: 242279
* [PowerPC] Extend physical register live range in PPCVSXFMAMutateHal Finkel2015-07-151-2/+15
| | | | | | | | | | | | | If the source of the copy that defines the addend is a physical register, then its existing live range may not extend to the FMA being mutated. Make sure we extend the live range of the register to meet the FMA because it will become its operand in this case. I don't have an independent test case, but it will be exposed by change to be committed shortly enabling the use of the machine combiner to do fadd/fmul reassociation, and will be covered by one of the associated regression tests. llvm-svn: 242278
* [MachineCombiner] Work with itinerariesHal Finkel2015-07-151-4/+9
| | | | | | | | | | | | MachineCombiner predicated its use of scheduling-based metrics on hasInstrSchedModel(), but useful conclusions can be drawn from pipeline itineraries as well. Almost all of the logic (except for resource tracking in preservesResourceLen) can be used if we have an itinerary, so enable it in that case as well. This will be used by the PowerPC backend in an upcoming commit. llvm-svn: 242277
* [AArch64] Fix problems in decoding generic MSR instructionsPetr Pavlu2015-07-151-0/+3
| | | | | | | | | Bitpatterns rejected by the decoder method of `MSR (immediate)` should be decoded as the `extended MSR (register)` instruction. Differential Revision: http://reviews.llvm.org/D7174 llvm-svn: 242276
* [PM/AA] Cleanup some loops to be range-based. NFC.Chandler Carruth2015-07-151-20/+19
| | | | llvm-svn: 242275
* AVX : Fix ISA disabling in case AVX512VL , some instructions should be ↵Igor Breger2015-07-152-30/+31
| | | | | | | | | | disabled only if AVX512BW present. Tests added. Differential Revision: http://reviews.llvm.org/D11122 llvm-svn: 242270
* Initial support for writing thin archives.Rafael Espindola2015-07-152-14/+25
| | | | llvm-svn: 242269
* Use enum instead of unsigned. NFC.Pete Cooper2015-07-152-2/+4
| | | | | | | | The unsigned opcode argument here was the result of BinaryOperator->getOpcode(). That returns a BinaryOps enum which is more accurate than passing around an unsigned. llvm-svn: 242265
* Use cast<> instead of dyn_cast to remove llvm_unreachable. NFC.Pete Cooper2015-07-151-4/+2
| | | | | | | | | | This code was checking if we are an ICmpInst or FCmpInst then throwing unreachable if we are neither. We must be one or the other, so use a cast on the FCmpInst case to ensure that we are that case. Then we can avoid having an unreachable but still catch an error if we ever had another subclass of CmpInst. llvm-svn: 242264
* Use another foreach loop. NFCPete Cooper2015-07-151-2/+1
| | | | llvm-svn: 242263
* Use getAnyExtOrTrunc helper instead of manually doing ext/trunc check. NFC.Pete Cooper2015-07-151-14/+5
| | | | | | | The code here was doing exactly what is already in getAnyExtOrTrunc(). Just use that method instead. llvm-svn: 242261
* Use getZExtOrTrunc helper instead of manually doing zext/trunc check. NFC.Pete Cooper2015-07-152-4/+2
| | | | | | | The code here was doing exactly what is already in getZExtOrTrunc(). Just use that method instead. llvm-svn: 242260
* [LoopUnrolling] Handle cast instructions.Michael Zolotukhin2015-07-151-0/+15
| | | | | | | | | During estimation of unrolling effect we should be able to propagate constants through casts. Differential Revision: http://reviews.llvm.org/D10207 llvm-svn: 242257
* Change conditional to assert. NFC.Pete Cooper2015-07-151-3/+2
| | | | | | | | This code was breaking from the case statement if the getStoreSizeInBits() value was not a multiple of 0. Given that the implementation returns getStoreSize() * 8, it can only be a multiple of 8. llvm-svn: 242255
* Use getStoreSize() instead of getStoreSizeInBits()/8. NFC.Pete Cooper2015-07-151-2/+1
| | | | | | | | The calls here were both to getStoreSizeInBits() which multiplies by 8. We then immediately divided by 8. Calling getStoreSize() returns the values we need without the extra arithmetic. llvm-svn: 242254
* Use a range loop.Rafael Espindola2015-07-141-4/+2
| | | | llvm-svn: 242250
* Use more foreach loops in SelectionDAG. NFCPete Cooper2015-07-144-42/+39
| | | | llvm-svn: 242249
* Create a wrapper pass for BlockFrequencyInfo.Wei Mi2015-07-143-36/+52
| | | | | | | | | | | | This is useful when we want to do block frequency analysis conditionally (e.g. only in PGO mode) but don't want to add one more pass dependence. Patch by congh. Approved by dexonsmith. Differential Revision: http://reviews.llvm.org/D11196 llvm-svn: 242248
* WebAssembly: fix build breakage.JF Bastien2015-07-145-8/+9
| | | | | | | | | | | | | | | Summary: processFunctionBeforeCalleeSavedScan was renamed to determineCalleeSaves and now takes a BitVector parameter as of rL242165, reviewed in http://reviews.llvm.org/D10909 WebAssembly is still marked as experimental and therefore doesn't build by default. It does, however, grep by default! I notice that processFunctionBeforeCalleeSavedScan is still mentioned in a few comments and error messages, which I also fixed. Reviewers: qcolombet, sunfish Subscribers: jfb, dsanders, hfinkel, MatzeB, llvm-commits Differential Revision: http://reviews.llvm.org/D11199 llvm-svn: 242242
* [PowerPC] Support symbolic targets in patchpointsHal Finkel2015-07-141-57/+71
| | | | | | | Follow-up r235483, with the corresponding support in PPC. We use a regular call for symbolic targets (because they're much cheaper than indirect calls). llvm-svn: 242239
* [InstCombine] Generalize sub of selects optimization to all BinaryOperatorsDavid Majnemer2015-07-142-26/+27
| | | | | | | This exposes further optimization opportunities if the selects are correlated. llvm-svn: 242235
* [LAA] Introduce RuntimePointerChecking::PointerInfo, NFCAdam Nemet2015-07-142-31/+35
| | | | | | | Turn this structure-of-arrays (i.e. the various pointer attributes) into array-of-structures. llvm-svn: 242219
* [LAA] Lift RuntimePointerCheck out of LoopAccessInfo, NFCAdam Nemet2015-07-144-55/+53
| | | | | | | | | I am planning to add more nested classes inside RuntimePointerCheck so all these triple-nesting would be hard to follow. Also rename it to RuntimePointerChecking (i.e. append 'ing'). llvm-svn: 242218
* [PowerPC] Use the ABI indirect-call protocol for patchpointsHal Finkel2015-07-141-1/+43
| | | | | | | | | | | | We used to take the address specified as the direct target of the patchpoint and did no TOC-pointer handling. This, however, as not all that useful, because MCJIT tends to create a lot of modules, and they have their own TOC sections. Thus, to call from the generated code to other generated code, you really need to switch TOC pointers. Make this work as expected, and under ELFv1, tread the address as the function descriptor address so that the correct TOC pointer can be loaded. llvm-svn: 242217
* Add support for reading members out of thin archives.Rafael Espindola2015-07-141-1/+22
| | | | | | | | | | For now the Archive owns the buffers of the thin archive members. This makes for a simple API, but all the buffers are destructed only when the archive is destructed. This should be fine since we close the files after mmap so we should not hit an open file limit. llvm-svn: 242215
* Add allnodes() iterator range to SelectionDAG. NFC.Pete Cooper2015-07-144-20/+12
| | | | | | | | | | | SelectionDAG already had begin/end methods for iterating over all the nodes, but didn't define an iterator_range for us in foreach loops. This adds such a method and uses it in some of the eligible places throughout the backends. llvm-svn: 242212
* Constify parameters in SelectionDAG methods. NFCPete Cooper2015-07-141-3/+3
| | | | llvm-svn: 242210
* Remove unnecessary .getNode() in SelectionDAG. NFC.Pete Cooper2015-07-141-22/+20
| | | | | | | | The simplify_type specialisation allows us to cast directly from SDValue to an SDNode* subclass so we don't need to pass a SDNode* to cast<>. llvm-svn: 242209
* Use more foreach loops in SelectionDAG. NFCPete Cooper2015-07-141-7/+6
| | | | llvm-svn: 242208
* MIR Serialization: Serialize the machine basic block live in registers.Alex Lorenz2015-07-144-1/+44
| | | | llvm-svn: 242204
* MIR Printer: move the function 'printReg'. NFC.Alex Lorenz2015-07-141-13/+13
| | | | | | | | This commit moves the function 'printReg' towards the start of the file so that it can be used by the conversion methods in MIRPrinter and not just the printing methods in MIPrinter. llvm-svn: 242203
* GVN: use a static array instead of regenerating it each time. NFC.Tim Northover2015-07-141-1/+1
| | | | llvm-svn: 242202
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