summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Updating inline saturate lanes for v62 version.Colin LeMahieu2017-03-161-1/+4
| | | | llvm-svn: 297920
* [libFuzzer] add a dummy LLVMFuzzerMutate to afl/afl_driver.cpp ↵Kostya Serebryany2017-03-151-0/+7
| | | | | | (https://github.com/google/oss-fuzz/issues/460) llvm-svn: 297919
* [libFuzzer] call __sanitizer_print_memory_profile with two paramsKostya Serebryany2017-03-152-2/+2
| | | | llvm-svn: 297916
* Remove redundant condition (PR32263). NFCI.Simon Pilgrim2017-03-151-1/+1
| | | | llvm-svn: 297915
* AMDGPU: Allow sinking of addressing modes for atomic_inc/decMatt Arsenault2017-03-152-7/+28
| | | | llvm-svn: 297913
* Revert "[libFuzzer] Use ChooseUnitIdxToMutate to pick item for crossover."Vitaly Buka2017-03-152-3/+3
| | | | | | | | Fails LLVMFuzzer.LLVMFuzzer.value-profile-strncmp.test. This reverts commit r297891. llvm-svn: 297912
* Revert "Revert "[PGO] Minor cleanup for count instruction in ↵Vitaly Buka2017-03-151-1/+4
| | | | | | | | | | SelectInstVisitor."" Previously reverted wrong revision. This reverts commit r297910. llvm-svn: 297911
* Revert "[PGO] Minor cleanup for count instruction in SelectInstVisitor."Vitaly Buka2017-03-151-4/+1
| | | | | | | | Fails LLVMFuzzer.LLVMFuzzer.value-profile-strncmp.test This reverts commit r297892. llvm-svn: 297910
* Fix build failure from r297897.Rong Xu2017-03-151-3/+3
| | | | llvm-svn: 297909
* Support: Simplify the CachePruning API. NFCI.Peter Collingbourne2017-03-152-13/+15
| | | | | | | | | Change the function that implements the pruning into a free function that takes the policy as a struct argument. Differential Revision: https://reviews.llvm.org/D31009 llvm-svn: 297907
* [StackColoring] Remove unused header file for post-order traversal. Update ↵Craig Topper2017-03-151-4/+2
| | | | | | comment that indicated we were using it when we really use a depth-first search. NFC llvm-svn: 297904
* CodeGenPrepare: Sink addressing modes for atomicsMatt Arsenault2017-03-151-1/+30
| | | | llvm-svn: 297903
* [llvm-pdbdump] Add support for diffing the String Table.Zachary Turner2017-03-151-1/+12
| | | | llvm-svn: 297901
* [pdb] Write the module info and symbol record streams.Zachary Turner2017-03-155-66/+193
| | | | | | | | | | | Previously we did not have support for writing detailed module information for each module, as well as the symbol records. This patch adds support for this, and in doing so enables the ability to construct minimal PDBs from just a few lines of YAML. A test is added to illustrate this functionality. llvm-svn: 297900
* Fix up grammar in a comment.Eric Christopher2017-03-151-1/+1
| | | | llvm-svn: 297898
* [PGO] Value profile for size of memory intrinsic callsRong Xu2017-03-152-13/+158
| | | | | | | | | This patch adds the value profile support to profile the size parameter of memory intrinsic calls: memcpy, memcmp, and memmov. Differential Revision: http://reviews.llvm.org/D28965 llvm-svn: 297897
* [PGO] Minor cleanup for count instruction in SelectInstVisitor.Rong Xu2017-03-151-1/+4
| | | | | | | | | | | | | | | | | Summary: NSIs can be double-counted by different operations in SelectInstVisitor. Sink the the update to VM_counting mode only. Also reset the value for each counting operation. Reviewers: davidxl Reviewed By: davidxl Subscribers: xur, llvm-commits Differential Revision: https://reviews.llvm.org/D30999 llvm-svn: 297892
* [libFuzzer] Use ChooseUnitIdxToMutate to pick item for crossover.Vitaly Buka2017-03-152-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D30683 llvm-svn: 297891
* NFC: Corrects comments that were supposed to go in with earlier commit.Adrian McCarthy2017-03-151-4/+5
| | | | llvm-svn: 297887
* [EarlyCSE] reduce indent; NFCISanjay Patel2017-03-151-21/+22
| | | | llvm-svn: 297886
* Introduce NativeEnumModules and NativeCompilandSymbolAdrian McCarthy2017-03-154-2/+115
| | | | | | | | | | | Together, these allow lldb-pdbdump to list all the modules from a PDB using a native reader (rather than DIA). Note that I'll probably be specializing NativeRawSymbol in a subsequent patch. Differential Revision: https://reviews.llvm.org/D30956 llvm-svn: 297883
* [DAGCombine] Bail out if can't create a vector with at least two elementsZvi Rackover2017-03-151-2/+5
| | | | | | | | | | | | | | | | Summary: Fixes pr32278 Reviewers: igorb, craig.topper, RKSimon, spatel, hfinkel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30978 llvm-svn: 297878
* [WebAssembly] Update format of 'names' section.Derek Schuff2017-03-151-6/+11
| | | | | | | | | | | | This change updates to the format of the 'names' sectionin the generated wasm binary to match the latest changesto the design and 'wabt'. Differential Revision: https://reviews.llvm.org/D30950 Patch by Sam Clegg llvm-svn: 297877
* [X86] Add missing BITREVERSE costs for SSE2 vectors and i8/i16/i32/i64 scalarsSimon Pilgrim2017-03-151-0/+19
| | | | | | Prep work for PR31810 llvm-svn: 297876
* [GlobalISel] Avoid translating synthetic constants to new G_CONSTANTS.Ahmed Bougacha2017-03-151-17/+20
| | | | | | | | | | | | | | | | | | | | | Currently, we create a G_CONSTANT for every "synthetic" integer constant operand (for instance, for the G_GEP offset). Instead, share the G_CONSTANTs we might have created by going through the ValueToVReg machinery. When we're emitting synthetic constants, we do need to get Constants from the context. One could argue that we shouldn't modify the context at all (for instance, this means that we're going to use a tad more memory if the constant wasn't used elsewhere), but constants are mostly harmless. We currently do this for extractvalue and all. For constant fcmp, this does mean we'll emit an extra COPY, which is not necessarily more optimal than an extra materialized constant. But that preserves the current intended design of uniqued G_CONSTANTs, and the rematerialization problem exists elsewhere and should be resolved with a single coherent solution. llvm-svn: 297875
* [GlobalISel][AArch64] Select ADDXri.Ahmed Bougacha2017-03-151-0/+4
| | | | | | | We're now able to select ADDWri thanks to the new complex pattern support. Extend that to ADDXri. llvm-svn: 297874
* AMDGPU: Fix unnecessary ands when packing f16 vectorsMatt Arsenault2017-03-156-6/+25
| | | | | | | | | computeKnownBits didn't handle fp_to_fp16 to report the high bits as 0. ARM maps the generic node to an instruction that does not modify the high bits of the register, so introduce a target node where the high bits are known 0. llvm-svn: 297873
* ARM: avoid clobbering register in v6 jump-table expansion.Tim Northover2017-03-153-2/+12
| | | | | | | | | | | If we got unlucky with register allocation and actual constpool placement, we could end up producing a tTBB_JT with an index that's already been clobbered. Technically, we might be able to fix this situation up with a MOV, but I think the constant islands pass is complex enough without having to deal with more weird edge-cases. llvm-svn: 297871
* [PGO] Refactor the code for value profile annotationRong Xu2017-03-151-29/+38
| | | | | | | | | This patch refactors the code for value profile annotation to facilitate of adding other kind of value profiles. Differential Revision: http://reviews.llvm.org/D30989 llvm-svn: 297870
* [GlobalISel] Insert translated switch icmp blocks after switch parent.Ahmed Bougacha2017-03-151-1/+2
| | | | | | | | | Now that we preserve the IR layout, we would end up with all the newly synthesized switch comparison blocks at the end of the function. Instead, use a hopefully more reasonable layout, with the comparison blocks immediately following the switch comparison blocks. llvm-svn: 297869
* [GlobalISel] Preserve IR block layout.Ahmed Bougacha2017-03-151-20/+26
| | | | | | | | | | | | | | It makes the output function layout more predictable; the layout has an effect on performance, we don't want it to be at the mercy of the translator's visitation order and such. The predictable output is also easier to digest. getOrCreateBB isn't appropriately named anymore, as it never needs to create anything. Rename it and extract the MBB creation logic out of it. A couple tests were sensitive to the order. Update them. llvm-svn: 297868
* AMDGPU: Minor SIAnnotateControlFlow cleanupsMatt Arsenault2017-03-151-31/+35
| | | | | | Newline fixes, early return, range loops. llvm-svn: 297865
* [YAML] When outputting, provide the ability to write default values.Zachary Turner2017-03-151-12/+5
| | | | | | | | | Previously, if you attempted to write a key/value pair and the value was equal to the key's default value, we would not output the value. Sometimes it is useful to be able to see this value in the output anyway. llvm-svn: 297864
* [CodeGen] Use APInt::setLowBits/setHighBits/setBitsFrom in more placesCraig Topper2017-03-152-25/+19
| | | | | | | | | | This patch replaces ORs with getHighBits/getLowBits etc. with setLowBits/setHighBits/setBitsFrom. In a few of the places we weren't ORing, but the KnownZero/KnownOne vectors were already initialized to zero. We exploit this in most places already there were just some that were inconsistent. Differential Revision: https://reviews.llvm.org/D30965 llvm-svn: 297860
* [GlobalISel] Remove dead member. NFC.Ahmed Bougacha2017-03-151-1/+0
| | | | llvm-svn: 297855
* CodeGen: Use the source filename as the argument to .file, rather than the ↵Peter Collingbourne2017-03-151-1/+1
| | | | | | | | | | | | | | | | module ID. Using the module ID here is wrong for a couple of reasons: 1) The module ID is not persisted, so we can end up with different object file contents given the same input file (for example if the same file is accessed via different paths). 2) With ThinLTO the module ID field may contain the path to a bitcode file, which is incorrect, as the .file argument is supposed to contain the path to a source file. Differential Revision: https://reviews.llvm.org/D30584 llvm-svn: 297853
* [SelectionDAG] Support BUILD_VECTOR implicit truncation in ↵Simon Pilgrim2017-03-151-3/+14
| | | | | | SelectionDAG::ComputeNumSignBits (PR32273) llvm-svn: 297852
* [PowerPC][Altivec] Add mfvrd and mffprd extended mnemonicNemanja Ivanovic2017-03-151-0/+12
| | | | | | | | | | | mfvrd and mffprd are both alias to mfvrsd. This patch enables correct parsing of the aliases, but we still emit a mfvrsd. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29177 llvm-svn: 297849
* Cyle -> Cycle; NFCISanjay Patel2017-03-153-8/+8
| | | | llvm-svn: 297846
* Revert "Refactor SimplifyCFG:canSinkInstructions [NFC]"Eric Liu2017-03-151-23/+23
| | | | | | This reverts commit r297839, which breaks Transforms/SimplifyCFG/sink-common-code.ll llvm-svn: 297845
* Revert "[Thumb1] Fix the bug when adding/subtracting -2147483648"Artyom Skrobov2017-03-151-4/+4
| | | | | | This reverts r297820 which apparently fails on A15 hosts. llvm-svn: 297842
* Reverted unintended commitSimon Pilgrim2017-03-151-2/+2
| | | | llvm-svn: 297841
* Fix Wint-in-bool-context warning (PR32248)Simon Pilgrim2017-03-151-2/+2
| | | | llvm-svn: 297840
* Refactor SimplifyCFG:canSinkInstructions [NFC]Aditya Kumar2017-03-151-23/+23
| | | | llvm-svn: 297839
* Reverting r297821 due to breaking lld test.Sam Parker2017-03-151-55/+33
| | | | llvm-svn: 297838
* [X86][SSE] Fixed shuffle MOVSS/MOVSD combining of all zeroable inputsSimon Pilgrim2017-03-151-4/+5
| | | | | | | | Turns out it can happen, so the assertion was too harsh Found during fuzz testing llvm-svn: 297833
* [Mips] Add support to match more patterns for DEXT and CINSPetar Jovanovic2017-03-155-40/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for recognizing more patterns to match to DEXT and CINS instructions. It finds cases where multiple instructions could be replaced with a single DEXT or CINS instruction. For example, for the following: define i64 @dext_and32(i64 zeroext %a) { entry: %and = and i64 %a, 4294967295 ret i64 %and } instead of generating: 0000000000000088 <dext_and32>: 88: 64010001 daddiu at,zero,1 8c: 0001083c dsll32 at,at,0x0 90: 6421ffff daddiu at,at,-1 94: 03e00008 jr ra 98: 00811024 and v0,a0,at 9c: 00000000 nop the following gets generated: 0000000000000068 <dext_and32>: 68: 03e00008 jr ra 6c: 7c82f803 dext v0,a0,0x0,0x20 Cases that are covered: DEXT: 1. and $src, mask where mask > 0xffff 2. zext $src zero extend from i32 to i64 CINS: 1. and (shl $src, pos), mask 2. shl (and $src, mask), pos 3. zext (shl $src, pos) zero extend from i32 to i64 Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D30464 llvm-svn: 297832
* Align cost model columns. NFCI.Simon Pilgrim2017-03-151-4/+4
| | | | llvm-svn: 297824
* [ARM] Fix for branch label disassembly for ThumbSam Parker2017-03-151-33/+55
| | | | | | | | | | | | | | | | | Different MCInstrAnalysis classes for arm and thumb mode, each with their own evaluateBranch implementation. I added a test case and fixed the coff-relocations test to use '<label>:' rather than '<label>' in the CHECK-LABEL entries, since the ones without the colon would match branch targets. Might be worth noticing that llvm-objdump does not lookup the relocation and thus assigns it a target depending on the encoded immediate which #0, so it thinks it branches to the next instruction. Committed on behalf of Andre Vieira (avieira). Differential Revision: https://reviews.llvm.org/D30943 llvm-svn: 297821
* [Thumb1] Fix the bug when adding/subtracting -2147483648Artyom Skrobov2017-03-151-4/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D30829 llvm-svn: 297820
OpenPOWER on IntegriCloud