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* [CMAKE] Update build on recent HaikuRenato Golin2016-02-261-1/+3
| | | | | | | | | This patch updates cmake build scripts to build on Haiku. It adds Haiku x86_64 to config.guess. Please consider reviewing. Pathc by Jérôme Duval. llvm-svn: 262038
* [x86, SSE] fold 'isPositive' vector integer operations (PR26701)Sanjay Patel2016-02-261-0/+42
| | | | | | | | | | | | | This is one of the cases shown in: https://llvm.org/bugs/show_bug.cgi?id=26701 Shift and negate is what InstCombine appears to prefer, so I've started with that pattern. Note that the 'pcmpeq' instructions are always generating the negative one for the actual 'pcmpgt' comparison in each case (side note: why isn't there an alias mnemonic for that?). Differential Revision: http://reviews.llvm.org/D17630 llvm-svn: 262036
* [WinEH] Fix funclet return block clobber mask placementReid Kleckner2016-02-261-2/+6
| | | | | | | | | | | | | | | | | | MBB slot index intervals are half open, not closed. getMBBEndIndex() returns the slot index of the start of the next block in layout order. Placing a register mask there is incorrect if the successor of the funclet return is not laid out after the return. Clang generates IR for catch bodies before generating the following normal code, so we never noticed this issue until the D frontend authors filed a bug about it. Instead, we can put the clobber mask on the last instruction of the funclet return block. We still aren't using a register mask operand on the CATCHRET instruction because it would cause PEI to spill all CSRs, including XMM regs, in the prologue. Fixes PR26679. llvm-svn: 262035
* [PM] Finish removing references to fix MSVC builds. Somehow adding baseChandler Carruth2016-02-261-8/+16
| | | | | | | | | classes changed whether the decltype of these expressions was a reference. I'm somewhat horrified why, and there may need to be a deeper fix on MSVC, but this should at least get the bots a step further. llvm-svn: 262008
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-264-303/+10
| | | | llvm-svn: 262007
* [PM] Speculative patch to try and fix MSVC's compilation.Chandler Carruth2016-02-261-1/+3
| | | | | | No idea why r262004 triggered this, but just trying to fix somehow. llvm-svn: 262006
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-264-10/+303
| | | | llvm-svn: 262005
* [PM] Introduce CRTP mixin base classes to help define passes andChandler Carruth2016-02-2623-79/+4
| | | | | | | | | | | | | | | | | analyses in the new pass manager. These just handle really basic stuff: turning a type name into a string statically that is nice to print in logs, and getting a static unique ID for each analysis. Sadly, the format of passes in anonymous namespaces makes using their names in tests really annoying so I've customized the names of the no-op passes to keep tests sane to read. This is the first of a few simplifying refactorings for the new pass manager that should reduce boilerplate and confusion. llvm-svn: 262004
* Initial test commit onlyChris Dewhurst2016-02-261-1/+0
| | | | llvm-svn: 262003
* [AMDGPU] Assembler: Basic support for MIMGNikolay Haustov2016-02-266-59/+202
| | | | | | | | | | | Add parsing and printing of image operands. Matches legacy sp3 assembler. Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last. Update SITargetLowering for new order. Add basic MC test. Update CodeGen tests. Review: http://reviews.llvm.org/D17574 llvm-svn: 261995
* [AArch64] Slight cleanup in FPLoadBalancingJames Molloy2016-02-261-2/+1
| | | | | | | | Instead of the convoluted if-statment we can just use getColor. This also fixes a bug where we relied upon the parity of tablegen-generated register indexes (instead of using the machine encoding). llvm-svn: 261990
* [X86] Null out some redundant patterns for masked vector register to ↵Craig Topper2016-02-261-10/+19
| | | | | | | | register moves. These can be accomplished with both aligned and unaligned opcodes. Currently aligned is what is being used so remove the redundant patterns for the unaligned versions. But don't do this for the byte and word vector types since they don't have aligned versions. llvm-svn: 261985
* [TableGen] Fix typos in comments. NFCCraig Topper2016-02-261-2/+2
| | | | llvm-svn: 261984
* [X86] Add test cases for r261977 and fix a grammatical error.Craig Topper2016-02-261-1/+1
| | | | llvm-svn: 261983
* [JumpThreading] Simplify Instructions first in ComputeValueKnownInPredecessors()Haicheng Wu2016-02-261-20/+35
| | | | | | This change tries to find more opportunities to thread over basic blocks. llvm-svn: 261981
* [X86] Remove a couple returns after llvm_unreachables. NFCCraig Topper2016-02-261-6/+2
| | | | llvm-svn: 261979
* [X86] Use inclusive ranges for XMM/YMM/ZMM registers in is32Extended and ↵Craig Topper2016-02-261-9/+9
| | | | | | isX86_64ExtendedReg. NFC llvm-svn: 261978
* [X86] Explicitly diagnose use of %xmm16-%xmm31, %ymm16-%ymm31 and ↵Craig Topper2016-02-261-1/+7
| | | | | | %zmm16-%zmm31 when AVX512 is not enabled in the asm parser. llvm-svn: 261977
* MachineCopyPropagation: Catch copies of the form A<-B;A<-BMatthias Braun2016-02-261-54/+71
| | | | | | Differential Revision: http://reviews.llvm.org/D17475 llvm-svn: 261966
* MachineCopyPropagation: Keep scanning through instructions with regmasksMatthias Braun2016-02-261-55/+55
| | | | | | | | | | | | | | | | | | | | | | | This also simplifies the code by removing the overly conservative NoInterveningSideEffect() function. This function checked: - That the two copies belong to the same block: We only process one block at a time and clear our maps in between it is impossible to find a copy from a different block. - There is no terminator between the two copy instructions: This is not allowed anyway (the MachineVerifier would complain) - Does not have instructions with hasUnmodeledSideEffects() or isCall() set: Even for those instructuction we must have all clobbers/defs of registers explicit as an operand. If the register is explicitely clobbered we would never come to the point of checking for NoInterveningSideEffect() anyway. (I also checked this with a temporary build of the test-suite with all potentially failing conditions in NoInterveningSideEffect() turned into asserts) Differential Revision: http://reviews.llvm.org/D17474 llvm-svn: 261965
* [LoopUnrollAnalyzer] Check that we're using SCEV for the same loop we're ↵Michael Zolotukhin2016-02-262-2/+2
| | | | | | | | | | | | | | simulating. Summary: Check that we're using SCEV for the same loop we're simulating. Otherwise, we might try to use the iteration number of the current loop in SCEV expressions for inner/outer loops IVs, which is clearly incorrect. Reviewers: chandlerc, hfinkel Subscribers: sanjoy, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D17632 llvm-svn: 261958
* Minor code cleanups. NFC.Junmo Park2016-02-261-3/+3
| | | | llvm-svn: 261955
* [sancov] Pruning full dominator blocks from instrumentation.Mike Aizatsky2016-02-261-4/+32
| | | | | | | | | | | | | | Summary: This is the first simple attempt to reduce number of coverage- instrumented blocks. If a basic block dominates all its successors, then its coverage information is useless to us. Ingore such blocks if santizer-coverage-prune-tree option is set. Differential Revision: http://reviews.llvm.org/D17626 llvm-svn: 261949
* [WinEH] Don't remove unannotated inline-asm callsDavid Majnemer2016-02-261-2/+3
| | | | | | | | Inline-asm calls aren't annotated with funclet bundle operands because they don't throw and cannot be inlined through. We shouldn't require them to bear an funclet bundle operand. llvm-svn: 261942
* Reformatted a comment to fit the 80 column limit. NFC.David L Kreitzer2016-02-251-2/+2
| | | | llvm-svn: 261916
* Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-253-0/+38
| | | | | | | | PassManager. NFC Differential Revision: http://reviews.llvm.org/D17571 llvm-svn: 261904
* Introduce DominanceFrontierAnalysis to the new PassManager to compute ↵Hongbin Zheng2016-02-257-21/+44
| | | | | | | | DominanceFrontier. NFC Differential Revision: http://reviews.llvm.org/D17570 llvm-svn: 261903
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-259-32/+78
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261902
* ARM: disallow pc as a base register in Thumb2 memory ops.Tim Northover2016-02-252-2/+2
| | | | | | | These should all be deferring to the "OP (literal)" variant according to the ARM ARM. llvm-svn: 261895
* Revert "Introduce analysis pass to compute PostDominators in the new pass ↵Hongbin Zheng2016-02-258-74/+28
| | | | | | | | manager. NFC" This reverts commit a3e5cc6a51ab5ad88d1760c63284294a4e34c018. llvm-svn: 261891
* Revert "Introduce DominanceFrontierAnalysis to the new PassManager to ↵Hongbin Zheng2016-02-257-44/+21
| | | | | | | | compute DominanceFrontier. NFC" This reverts commit 109c38b2226a87b0be73fa7a0a8c1a81df20aeb2. llvm-svn: 261890
* Revert "Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-253-38/+0
| | | | | | | | PassManager. NFC" This reverts commit 8228b4d374edeb4cc0c5fddf6e1ab876918ee126. llvm-svn: 261889
* rangify; NFCISanjay Patel2016-02-251-54/+43
| | | | llvm-svn: 261888
* [AArch64] Clean up callee-save CFI emission. NFC.Geoff Berry2016-02-252-46/+9
| | | | | | | | | | | | | | | | | | | Summary: Avoid special case for FP, LR CFI emission and just allow general AArch64FrameLowering::emitCalleeSavedFrameMoves() to handle them. Also, stop recalculating the stack offsets in emitCalleeSavedFrameMoves() since we can just reuse the previously calculated offset stored in the MachineFrameInfo. Depends on D17000 Reviewers: t.p.northover, rengolin, mcrosier, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D17004 llvm-svn: 261885
* Introduce RegionInfoAnalysis, which compute Region Tree in the new ↵Hongbin Zheng2016-02-253-0/+38
| | | | | | | | PassManager. NFC Differential Revision: http://reviews.llvm.org/D17571 llvm-svn: 261884
* Introduce DominanceFrontierAnalysis to the new PassManager to compute ↵Hongbin Zheng2016-02-257-21/+44
| | | | | | | | DominanceFrontier. NFC Differential Revision: http://reviews.llvm.org/D17570 llvm-svn: 261883
* Introduce analysis pass to compute PostDominators in the new pass manager. NFCHongbin Zheng2016-02-258-28/+74
| | | | | | Differential Revision: http://reviews.llvm.org/D17537 llvm-svn: 261882
* [AMDGPU] Disassembler: Support for all VOP1 instructions.Nikolay Haustov2016-02-253-62/+242
| | | | | | | | | | | | | | | Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 llvm-svn: 261878
* AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . ↵Igor Breger2016-02-254-97/+103
| | | | | | | | Change memory operand parser handling. Differential Revision: http://reviews.llvm.org/D17564 llvm-svn: 261862
* [mips][microMIPS] Implement DINSU, DINSM, DINS instructionsHrvoje Varga2016-02-255-9/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
* [AMDGPU] Assembler: Simplify handling of optional operandsNikolay Haustov2016-02-253-75/+77
| | | | | | | | | | | | | | | | | | | | | | Resubmit with index problem fixed. Verified with valgrind. Prepare to support DPP encodings. For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands. However this means that when parsing instruction which has no mnemonic prefix, we cannot add both default values for VOP3 and for DPP optional operands to OperandVector - neither instructions would match. So add default values for optional operands to MCInst during conversion instead. Mark more operands as IsOptional = 1 in .td files. Do not add default values for optional operands to OperandVector in AMDGPUAsmParser. Add default values for optional operands during conversion using new helper addOptionalImmOperand. Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one. Separate cvtFlat and cvtFlatAtomic. Fix CNDMASK_B32 definition to have no modifiers. Review: http://reviews.llvm.org/D17445 llvm-svn: 261856
* [X86][SSE3] Added combine support for MOVDDUP/MOVSHDUP/MOVSLDUP target shufflesSimon Pilgrim2016-02-251-0/+3
| | | | | | Now that PerformShuffleCombine can handle unary shuffles. llvm-svn: 261843
* Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands"NAKAMURA Takumi2016-02-253-79/+75
| | | | | | It brought undefined behavior. llvm-svn: 261839
* PM: Implement a basic loop pass managerJustin Bogner2016-02-254-2/+184
| | | | | | | | | | | This creates the new-style LoopPassManager and wires it up with dummy and print passes. This version doesn't support modifying the loop nest at all. It will be far easier to discuss and evaluate the approaches to that with this in place so that the boilerplate is out of the way. llvm-svn: 261831
* Optimized loading (zextload) of i1 value from memory.Elena Demikhovsky2016-02-252-13/+6
| | | | | | | | | | | This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793. Extra "and" causes performance degradation. We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits. Differential Revision: http://reviews.llvm.org/D17541 llvm-svn: 261828
* IR: Make the X / undef -> undef fold match the commentJustin Bogner2016-02-251-1/+1
| | | | | | | | | | | | | | | | The constant folding for sdiv and udiv has a big discrepancy between the comments and the code, which looks like a typo. Currently, we're folding X / undef pretty inconsistently: 0 / undef -> undef C / undef -> 0 undef / undef -> 0 Whereas the comments state we do X / undef -> undef. The logic that returns zero is actually commented as doing undef / X -> 0, despite that the LHS isn't undef in many of the cases that hit it. llvm-svn: 261813
* [CodeGenPrepare] Remove load-based heuristicJunmo Park2016-02-251-11/+0
| | | | | | | | | | | | | | Summary: Both the hardware and LLVM have changed since 2012. Now, load-based heuristic don't show big differences any more on OoO cores. There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5). Reviewers: spatel, zansari Differential Revision: http://reviews.llvm.org/D16836 llvm-svn: 261809
* Detecte vector reduction operations just before instruction selection.Cong Hou2016-02-241-0/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | (This is the second attemp to commit this patch, after fixing pr26652 & pr26653). This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and for such operations we have freedom to reorganize the elements of the result as long as the reduction of them stay unchanged. This will enable some reduction pattern recognition during instruction combine such as SAD/dot-product on X86. A flag is added to SDNodeFlags to mark those vector reduction nodes to be checked during instruction combine. To detect those vector reductions, we search def-use chains starting from the given instruction, and check if all uses fall into two categories: 1. Reduction with another vector. 2. Reduction on all elements. in which 2 is detected by recognizing the pattern that the loop vectorizer generates to reduce all elements in the vector outside of the loop, which includes several ShuffleVector and one ExtractElement instructions. Differential revision: http://reviews.llvm.org/D15250 llvm-svn: 261804
* Add capability to push/pop DFI in MCStreamer. NFCAmaury Sechet2016-02-241-2/+6
| | | | | | | | | | | | Summary: This is extracted from D17555 Reviewers: davidxl, reames, sanjoy, MatzeB, pete Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17579 llvm-svn: 261796
* [asan] Do not instrument globals in the special "LLVM" sectionsAnna Zaks2016-02-241-1/+1
| | | | llvm-svn: 261794
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