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* [ValueTracking] fix typos, formatting; NFCSanjay Patel2017-10-161-11/+10
| | | | llvm-svn: 315909
* [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the ↵Alexander Timofeev2017-10-161-11/+13
| | | | | | | | dead one Differential revision: https://reviews.llvm.org/D38754 llvm-svn: 315908
* [mips][micromips] Fix (dis)assembly of bc1(t|f)Simon Dardis2017-10-163-14/+21
| | | | | | | | | | | | Previously these instructions were marked codegen only and had an under-specified instruction description that did not record the fcc register. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D38847 llvm-svn: 315905
* ISel type legalizer: debug messages. NFC.Sjoerd Meijer2017-10-162-4/+17
| | | | | | | | | | | Minor addition and follow up of r314773 and r311533: this adds more debug messages to the type legalizer. For each node, it dumps legalization info for results and operands nodes, rather than just the final legalized node. Differential Revision: https://reviews.llvm.org/D38726 llvm-svn: 315904
* Fix or vs || typo.Simon Pilgrim2017-10-161-1/+1
| | | | llvm-svn: 315903
* [mips] Provide alternate predicates for constant synthesisStefan Maksimovic2017-10-162-17/+30
| | | | | | | Ordering of patterns should not be of importance anymore since the predicates used are mutually exclusive now. llvm-svn: 315901
* [PowerPC] fix up in sign-/zero-extension eliminationHiroshi Inoue2017-10-161-0/+2
| | | | | | This patch fixes a potential problem in my previous commit (https://reviews.llvm.org/rL315888) by adding a null check. llvm-svn: 315900
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-169-171/+264
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [llvm-dwarfdump] - Teach tool to parse DW_CFA_GNU_args_size.George Rimar2017-10-161-0/+1
| | | | | | | | | Currently llvm-dwarfdump runs into llvm_unreachable when faces DW_CFA_GNU_args_size. Patch implements the support. Differential revision: https://reviews.llvm.org/D38879 llvm-svn: 315897
* Revert rL315894, "SLPVectorizer.cpp: Try to appease stage2-3 difference. ↵NAKAMURA Takumi2017-10-161-9/+23
| | | | | | (D38586)" llvm-svn: 315896
* Move folding of icmp with zero after checking for min/max idioms.Nikolai Bozhenov2017-10-162-11/+23
| | | | | | | | | | | | | | | | | | | | | Summary: The following transformation for cmp instruction: icmp smin(x, PositiveValue), 0 -> icmp x, 0 should only be done after checking for min/max to prevent infinite looping caused by a reverse canonicalization. That is why this transformation was moved to place after the mentioned check. Reviewers: spatel, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38934 Patch by: Artur Gainullin <artur.gainullin@intel.com> llvm-svn: 315895
* SLPVectorizer.cpp: Try to appease stage2-3 difference. (D38586)NAKAMURA Takumi2017-10-161-23/+9
| | | | llvm-svn: 315894
* [aarch64][globalisel] Fix a crash in selectAddrModeIndexed() caused by ↵Daniel Sanders2017-10-161-1/+5
| | | | | | | | | | incorrect G_FRAME_INDEX handling The wrong operand was being rendered to the result instruction. The crash was detected by Bitcode/simd_ops/AArch64_halide_runtime.bc llvm-svn: 315890
* bpf: fix bug on silently truncating 64-bit immediateYonghong Song2017-10-162-3/+7
| | | | | | | | | | | | | | | | We came across an llvm bug when compiling some testcases that 64-bit immediates are silently truncated into 32-bit and then packed into BPF_JMP | BPF_K encoding. This caused comparison with wrong value. This bug looks to be introduced by r308080. The Select_Ri pattern is supposed to be lowered into J*_Ri while the latter only support 32-bit immediate encoding, therefore Select_Ri should have similar immediate predicate check as what J*_Ri are doing. Reported-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 315889
* [PowerPC] Eliminate sign- and zero-extensions if already sign- or zero-extendedHiroshi Inoue2017-10-166-0/+506
| | | | | | | | | | | | | | | | | | This patch enables redundant sign- and zero-extension elimination in PowerPC MI Peephole pass. If the input value of a sign- or zero-extension is known to be already sign- or zero-extended, the operation is redundant and can be eliminated. One common case is sign-extensions for a method parameter or for a method return value; they must be sign- or zero-extended as defined in PPC ELF ABI. For example of the following simple code, two extsw instructions are generated before the invocation of int_func and before the return. With this patch, both extsw are eliminated. void int_func(int); void ii_test(int a) { if (a & 1) return int_func(a); } Such redundant sign- or zero-extensions are quite common in many programs; e.g. I observed about 60,000 occurrences of the elimination while compiling the LLVM+CLANG. Differential Revision: https://reviews.llvm.org/D31319 llvm-svn: 315888
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-163-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-163-176/+0
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-163-0/+176
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [Hexagon] Add LLVM_ATTRIBUTE_UNUSED to operator<<, NFCKrzysztof Parzyszek2017-10-161-0/+8
| | | | | | This should silence "unused function" warnings. llvm-svn: 315883
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-152-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-152-9/+6
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-152-6/+9
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [X86] Remove the SlowBTMem feature flag entirelyCraig Topper2017-10-154-66/+31
| | | | | | Turns out we have no patterns on the instructions that were using this feature flag for other reasons. These instructions are slow on all modern CPUs so it seems unlikely that we will spend any effort supporting these instructions going forward. So we might as well just kill of the feature flag and just fix up the comments. llvm-svn: 315862
* [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom ↵Craig Topper2017-10-152-59/+15
| | | | | | | | | | | | | | | | | | | lowering. Summary: This was impeding our ability to combine the extending shuffles with other shuffles as you can see from the test changes. There's one special case that needed to be added to use VZEXT directly for v8i8->v8i64 since the custom lowering requires v64i8. Reviewers: RKSimon, zvi, delena Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38714 llvm-svn: 315860
* [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and ↵Craig Topper2017-10-151-6/+13
| | | | | | | | | | | | | | | | Knights Landing CPUs. Summary: I see nothing in Agner Fog's tables to indicate that this improved between Ivy Bridge and Haswell. It's also set for all Atom CPUs so I assume KNL should have it too. Reviewers: RKSimon, zvi, gadi.haber Reviewed By: gadi.haber Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38890 llvm-svn: 315859
* revert r314984: revert r314698 - [InstCombine] remove one-use restriction ↵Sanjay Patel2017-10-151-6/+6
| | | | | | | | | for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1) Recommitting r314698. The bug exposed by this change should be fixed with: https://reviews.llvm.org/rL315579 llvm-svn: 315857
* [SimplifyCFG] use range-for-loops, tidy; NFCISanjay Patel2017-10-151-20/+10
| | | | | | | There seems to be something missing here as shown in PR34471: https://bugs.llvm.org/show_bug.cgi?id=34471 llvm-svn: 315855
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-1597-148/+148
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* [MergeFunctions] Merge small functions if possible without a thunk.whitequark2017-10-151-12/+10
| | | | | | | | | | This can result in significant code size savings in some cases, e.g. an interrupt table all filled with the same assembly stub in a certain Cortex-M BSP results in code blowup by a factor of 2.5. Differential Revision: https://reviews.llvm.org/D34806 llvm-svn: 315853
* [MergeFunctions] Replace all uses of unnamed_addr functions.whitequark2017-10-151-3/+9
| | | | | | | | | This reduces code size for constructs like vtables or interrupt tables that refer to functions in global initializers. Differential Revision: https://reviews.llvm.org/D34805 llvm-svn: 315852
* [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve ↵Amjad Aboud2017-10-151-0/+31
| | | | | | | | PR34565 Differential Revision: https://reviews.llvm.org/D38359 llvm-svn: 315851
* [LoopInfo][Refactor] Make SetLoopAlreadyUnrolled a member function of the ↵Hongbin Zheng2017-10-153-67/+35
| | | | | | | | | | Loop Pass, NFC. This avoid code duplication and allow us to add the disable unroll metadata elsewhere. Differential Revision: https://reviews.llvm.org/D38928 llvm-svn: 315850
* [X86] Lower vselect with constant condition to vector_shuffle even with ↵Craig Topper2017-10-151-5/+5
| | | | | | | | | | | | | | | | | | | AVX512 instructions. Summary: It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register. It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day. Reviewers: RKSimon, delena, zvi Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38932 llvm-svn: 315849
* Remove unused variablesVitaly Buka2017-10-155-5/+2
| | | | llvm-svn: 315847
* [Hexagon] Mark RangeTree::dump() with LLVM_DUMP_METHOD.Davide Italiano2017-10-141-1/+1
| | | | | | | GCC otherwise emits a "defined but not used" warning on the member function. llvm-svn: 315838
* AMDGPU: Don't use TargetStreamer if it has not been initializedKonstantin Zhuravlyov2017-10-142-10/+16
| | | | | | | | | | Fixes cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl test after r315808 We may hit few other similar issues, but I want to discuss good solution offline. llvm-svn: 315830
* [X86][SSE] Don't attempt to reduce the imul vector width of odd sized ↵Simon Pilgrim2017-10-141-1/+4
| | | | | | vectors (PR34947) llvm-svn: 315825
* Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for ↵Bruno Cardoso Lopes2017-10-141-32/+4
| | | | | | | | | COPY" This reverts commit r315781, breaks: http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882 llvm-svn: 315823
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-145-94/+121
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* Pull out repeated calls to VT.getVectorNumElements(). NFCI.Simon Pilgrim2017-10-141-10/+11
| | | | llvm-svn: 315818
* Use DAG::getBitcast() helper. NFCI.Simon Pilgrim2017-10-141-4/+4
| | | | llvm-svn: 315815
* AMDGPU: Improve note directive verification in assemblerKonstantin Zhuravlyov2017-10-141-1/+19
| | | | | | | | | | - Do not allow amd_amdgpu_isa directives on non-amdgcn architectures - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes Differential Revision: https://reviews.llvm.org/D38750 llvm-svn: 315812
* AMDGPU: Do not emit deprecated notes for code object v3Konstantin Zhuravlyov2017-10-146-11/+40
| | | | | | Differential Revision: https://reviews.llvm.org/D38749 llvm-svn: 315810
* AMDGPU: Add support for isa version noteKonstantin Zhuravlyov2017-10-146-10/+97
| | | | | | | | | | - Emit NT_AMD_AMDGPU_ISA - Add assembler parsing for isa version directive - If isa version directive does not match command line arguments, then return error Differential Revision: https://reviews.llvm.org/D38748 llvm-svn: 315808
* [X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))Simon Pilgrim2017-10-141-0/+39
| | | | | | | | If we are applying a byte mask to a value extracted from a shuffle, see if we can combine the mask into shuffle. Fixes the last issue with PR22415 llvm-svn: 315807
* [X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.Craig Topper2017-10-142-1/+19
| | | | llvm-svn: 315802
* [X86] Add AVX512 versions of VCVTPD2PS to load folding tables.Craig Topper2017-10-141-0/+3
| | | | llvm-svn: 315801
* [X86] Add patterns for vzmovl+cvtpd2ps with a load.Craig Topper2017-10-142-12/+24
| | | | llvm-svn: 315800
* [X86] Remove some patterns for bitcasted alignednonedtemporalloads.Craig Topper2017-10-141-18/+0
| | | | | | These select the same instruction as the non-bitcasted pattern. So this provides no additional value. llvm-svn: 315799
* [X86] Remove unnecessary bitconverts as the root of patterns for zero ↵Craig Topper2017-10-141-4/+4
| | | | | | | | extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr. We don't need a bitconvert as a root pattern in these cases. The types in the other parts of the pattern are sufficient to express the behavior of these instructions. llvm-svn: 315798
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