| Commit message (Collapse) | Author | Age | Files | Lines | 
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llvm-svn: 96440
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It's not clear why this is really required, but it was explicitly
added in r48808 with no real explanation or rdar #.
llvm-svn: 96438
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This pass is supposed to be run on the linked .bc module.
It traveses the module call graph twice. Once starting from the main function
and marking each reached function as "ML". Again, starting from the ISR
and cloning any reachable function that was marked as "ML". After cloning
the function, it remaps all the call sites in IL functions to call the
cloned functions. 
Currently only marking is being done.
llvm-svn: 96435
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llvm-svn: 96432
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llvm-svn: 96429
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have overflowed.
llvm-svn: 96428
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64 bits, fixing a variety of problems.
llvm-svn: 96421
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indentation.  No functional changes.
llvm-svn: 96418
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llvm-svn: 96410
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into a roundss intrinsic, producing a cyclic dag.  The root cause
of this is badness handling ComplexPattern nodes in the old dagisel
that I noticed through inspection.  Eliminate a copy of the of the
code that handled ComplexPatterns by making EmitChildMatchCode call
into EmitMatchCode.
llvm-svn: 96408
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build failures due to my fix for pr6111.
llvm-svn: 96402
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llvm-svn: 96401
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llvm-svn: 96399
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llvm-svn: 96395
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llvm-svn: 96393
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If there exists a use of a build_vector that's the bitwise complement of the mask,
then transform the node to
(and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).
Since this transformation is only useful when 1) the given build_vector will
become a load from constpool, and 2) (and (xor x -1), y) matches to a single
instruction, I decided this is appropriate as a x86 specific transformation.
rdar://7323335
llvm-svn: 96389
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llvm-svn: 96388
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llvm-svn: 96387
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non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.
Add documentation for !nontemporal metadata.
Add a simpler movnt testcase.
llvm-svn: 96386
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to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
llvm-svn: 96384
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set of Defs.
llvm-svn: 96383
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llvm-svn: 96382
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They won't work with the new ISel mechanism, as Requires predicates are no
longer allowed to reference the node being selected. Moving the predicate to
the patterns instead solves the problem.
This patch handles ARM mode. Thumb2 will follow.
llvm-svn: 96381
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o Store Return State (SRSW, SRS)
o Load/Store Coprocessor (LDC/STC and friends)
o MSR (immediate)
llvm-svn: 96380
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llvm-svn: 96378
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terminator's list of successors.
llvm-svn: 96377
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llvm-svn: 96372
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llvm-svn: 96370
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branch in ARM v4 code, since it gets clobbered by the return address before
it is used.  Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
llvm-svn: 96360
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methods to try to have the type predicates be more logically positioned.
llvm-svn: 96349
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and T->isPointerTy().  Convert most instances of the first form to the second form.
Requested by Chris.
llvm-svn: 96344
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llvm-svn: 96343
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llvm-svn: 96337
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not the end of the field, fixing rdar://7651978
llvm-svn: 96330
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Currently, whether a function is ISR or not is encoded in the section attribute for that function.
llvm-svn: 96322
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elimination.  Before a DBG_VALUE could affect codegen.
The solution here is imperfect and not final.
llvm-svn: 96318
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llvm-gcc but has been replaced with pad argument which don't need any
special backend support.
llvm-svn: 96312
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as it also peeks at which registers are being used by other uses. This
makes LSR less sensitive to use-list order.
llvm-svn: 96308
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at older buildbot messages, I see the failure predates
this patch.
llvm-svn: 96307
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finished.
llvm-svn: 96304
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but it's harder to believe it's the other candidate,
so reverting.  Temporarily I hope.
llvm-svn: 96303
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strict about the requirements.
llvm-svn: 96301
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We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
llvm-svn: 96297
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llvm-svn: 96295
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llvm-svn: 96294
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llvm-svn: 96292
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llvm-svn: 96290
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llvm-svn: 96289
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llvm-svn: 96288
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early beginning! The "z" CIE augmentation mark indicates that there is an extra word containing the size of augmentation section. However, even for frames w/o any augmentation data we emitted size uleb! (this is the case of "unwinding through C code"). Thus frame moves information was emitterd completely wrong.
llvm-svn: 96287
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