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* Expand rotate instructions on sparcv9 as well.Roman Divacky2013-11-121-0/+2
| | | | llvm-svn: 194500
* Simplify operand folding when rematerializing a load.Andrew Trick2013-11-121-1/+6
| | | | | | | | | | | | We already know how to fold a reload from a frameindex without analyzing the load instruction. Generalize this to handle any frameindex load. This streamlines the logic for rematerializing loads from stack arguments. As a side effect, it allows stackmaps to record a stack argument location without spilling it. Verified no effect on codegen for llvm test-suite. llvm-svn: 194497
* R600: Reenable llvm.R600.load.input/interp.input for compatibilityVincent Lejeune2013-11-122-0/+47
| | | | llvm-svn: 194484
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-122-9/+51
| | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. llvm-svn: 194476
* SimplifyCFG: Use existing constant folding logic when forming switch tables.Benjamin Kramer2013-11-121-31/+20
| | | | | | Both simpler and more powerful than the hand-rolled folding logic. llvm-svn: 194475
* [mips][msa] Fix buildbot failures caused by an unused variable when ↵Daniel Sanders2013-11-121-2/+1
| | | | | | assertions are disabled. llvm-svn: 194472
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-129-38/+161
| | | | | | not intrinsics) llvm-svn: 194471
* [ARM] Add support for FP_HP_extension build attributeBradley Smith2013-11-122-1/+7
| | | | llvm-svn: 194470
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-122-70/+216
| | | | | | normal IR (i.e. not intrinsics) llvm-svn: 194469
* XCore target: fix bug in aligning 'byval i8*' on the stackRobert Lytton2013-11-121-1/+1
| | | | llvm-svn: 194466
* Add XCore support for ATOMIC_FENCE.Robert Lytton2013-11-123-1/+25
| | | | | | | | | | ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There is no need to emit an instructions since the XCore provides sequential consistency. Original patch by Richard Osborne llvm-svn: 194464
* XCore target: return error for unsupported alignmentRobert Lytton2013-11-121-0/+4
| | | | llvm-svn: 194463
* Change data structure to memorize computed result in ScalarEvolutionWan Xiaofei2013-11-121-22/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace std::map with SmallVector to memorize the cached result since SCEV usually belongs to little Loop/BB Linear scan on SmallVector is faster than std::map. Code reviewer : Andrew Trick. Test result : Pass Unit Test & LLVM Test Suite 401.bzip2 0.425721 0.419981 101.37% 403.gcc 24.53855 24.2667 101.12% 429.mcf 0.060847 0.059944 101.51% 433.milc 0.646009 0.636119 101.55% 444.namd 1.383928 1.370614 100.97% 445.gobmk 5.836575 5.800225 100.63% 450.soplex 1.911257 1.895963 100.81% 456.hmmer 1.039565 1.032534 100.68% 458.sjeng 0.897401 0.885567 101.34% 464.h264ref 3.645908 3.577991 101.90% 470.lbm 0.049456 0.048398 102.19% 471.omnetpp 5.638575 5.60435 100.61% bitmnp01 0.045738 0.045291 100.99% cjpegv2data 0.304359 0.302833 100.50% idctrn01 0.046433 0.045763 101.46% quake2 4.534416 4.4952 100.87% quake 2.688566 2.659208 101.10% xcsoar 12.42545 12.30385 100.99% linpack 0.038739 0.03803 101.86% matrix01 0.053564 0.0528 101.45% nbench 0.402867 0.395803 101.78% tblook01 0.021265 0.021015 101.19% ttsprk01 0.066384 0.065566 101.25% llvm-svn: 194459
* Correct a glitch in r194424 which may invalidate iterator.Shuxin Yang2013-11-121-1/+3
| | | | llvm-svn: 194457
* llvm-cov: Added call to update run/program counts.Yuchen Wu2013-11-121-0/+8
| | | | | | Also updated test files that were generated from this change. llvm-svn: 194453
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-122-2/+64
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-123-5/+26
| | | | | | | | | | | This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. llvm-svn: 194442
* Extract a bc attr parsing helper that returns Attribute::None on errorReid Kleckner2013-11-121-78/+49
| | | | | | | The parsing method still returns llvm::error_code for consistency with other parsing methods. Minor cleanup, no functionality change. llvm-svn: 194437
* Lower X86::MORESTACK_RET and X86::MORESTACK_RET_RESTORE_R10 inLang Hames2013-11-111-12/+12
| | | | | | | | | | | | | | X86AsmPrinter::EmitInstruction, rather than X86MCInstLower::Lower. The aim is to improve the reusability of the X86MCInstLower class by making it more function-like. The X86::MORESTACK_RET_RESTORE_R10 pseudo broke the function model by emitting an extra instruction to the MCStreamer attached to the AsmPrinter. The patch should have no impact on generated code. llvm-svn: 194431
* Fix the recently added anyregcc convention to handle spilled operands.Andrew Trick2013-11-111-1/+10
| | | | | | | | | | | | Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. llvm-svn: 194428
* Print new JavaScript calling conventions symbolically.Andrew Trick2013-11-111-0/+2
| | | | llvm-svn: 194427
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-114-41/+39
| | | | llvm-svn: 194425
* Fix PR17952.Shuxin Yang2013-11-111-6/+175
| | | | | | | | | | | | | | | | | | | | | | | The symptom is that an assertion is triggered. The assertion was added by me to detect the situation when value is propagated from dead blocks. (We can certainly get rid of assertion; it is safe to do so, because propagating value from dead block to alive join node is certainly ok.) The root cause of this bug is : edge-splitting is conducted on the fly, the edge being split could be a dead edge, therefore the block that split the critial edge needs to be flagged "dead" as well. There are 3 ways to fix this bug: 1) Get rid of the assertion as I mentioned eariler 2) When an dead edge is split, flag the inserted block "dead". 3) proactively split the critical edges connecting dead and live blocks when new dead blocks are revealed. This fix go for 3) with additional 2 LOC. Testing case was added by Rafael the other day. llvm-svn: 194424
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-1/+1
| | | | | | | the floating point register mode. llvm-svn: 194423
* CalcSpillWeights: allow overidding the spill weight normalizing functionArnaud A. de Grandmaison2013-11-111-3/+4
| | | | | | | | This will enable the PBQP register allocator to provide its own normalizing function. No functionnal change. llvm-svn: 194417
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-112-0/+3
| | | | llvm-svn: 194416
* Fixing a problem with iterator validity in ↵Andrew Kaylor2013-11-111-2/+12
| | | | | | RuntimeDyldImpl::resolveExternalSymbols llvm-svn: 194415
* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ↵Justin Holewinski2013-11-111-13/+38
| | | | | | of function parameters llvm-svn: 194410
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-111-1/+1
| | | | llvm-svn: 194409
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-10/+21
| | | | | | source operands, a vector, an element to insert, and a shift amount. llvm-svn: 194406
* CalcSpillWeights: give a better describing name to calculateSpillWeightsArnaud A. de Grandmaison2013-11-115-9/+10
| | | | | | | | Besides, this relates it more obviously to the VirtRegAuxInfo::calculateSpillWeightAndHint. No functionnal change. llvm-svn: 194404
* Unify the adding of enumerators with the construction of the enumeration.Eric Christopher2013-11-112-23/+25
| | | | llvm-svn: 194401
* Formatting.Eric Christopher2013-11-111-9/+8
| | | | llvm-svn: 194400
* 80-col.Eric Christopher2013-11-111-5/+7
| | | | llvm-svn: 194399
* Just pass the DIComposite type by value instead of by pointer.Eric Christopher2013-11-112-6/+6
| | | | llvm-svn: 194398
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-3/+25
| | | | | | instructions. llvm-svn: 194394
* Vector forms of SHL, SRA, and SRL can be constant folded using ↵Daniel Sanders2013-11-111-0/+18
| | | | | | | | | | | | | | SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 llvm-svn: 194393
* Move debug message in vectorizerRenato Golin2013-11-111-4/+1
| | | | | | No functional change, just better reporting. llvm-svn: 194388
* Add PPC option for full register names in asmHal Finkel2013-11-111-0/+10
| | | | | | | | | | | | | | | | | | | | | On non-Darwin PPC systems, we currently strip off the register name prefix prior to instruction printing. So instead of something like this: mr r3, r4 we print this: mr 3, 4 The first form is the default on Darwin, and is understood by binutils, but not yet understood by our integrated assembler. Once our integrated-as understands full register names as well, this temporary option will be replaced by tying this functionality to the verbose-asm option. The numeric-only form is compatible with legacy assemblers and tools, and is also gcc's default on most PPC systems. On the other hand, it is harder to read, and there are some analysis tools that expect full register names. llvm-svn: 194384
* Simplify code. No functionality change.Benjamin Kramer2013-11-111-5/+1
| | | | llvm-svn: 194383
* [msan] Propagate origin for insertvalue, extractvalue.Evgeniy Stepanov2013-11-111-2/+2
| | | | llvm-svn: 194374
* [NVPTX] Blacklist TailDuplicate passJustin Holewinski2013-11-111-0/+1
| | | | | | | | This causes issues with virtual registers. We will likely need to fix TailDuplicate in the future, or introduce a new version that plays nicely with vregs. llvm-svn: 194373
* AArch64: refactor vector list creation to be more uniformTim Northover2013-11-111-101/+55
| | | | | | | | | | | Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a special register-class to deal with the constraints, and C++ code to support selection. However, that C++ code can be made reasonably uniform to simplify the selection process. Hence this patch. No functionality change, so no tests. llvm-svn: 194361
* CalculateSpillWeights does not need to be a passArnaud A. de Grandmaison2013-11-105-29/+14
| | | | | | | | | | Based on discussions with Lang Hames and Jakob Stoklund Olesen at the hacker's lab, and in the light of upcoming work on the PBQP register allocator, it was though that CalcSpillWeights does not need to be a pass. This change will enable to customize / tune the spill weight computation depending on the allocator. Update the documentation style while there. No functionnal change. llvm-svn: 194356
* Revert "Resurrect r191017 " GVN proceeds in the presence of dead code" plus ↵Bill Wendling2013-11-101-168/+6
| | | | | | | | | | | | | a fix to PR17307 & 17308." This causes PR17852. This reverts commit d93e8a06b2ca09ab18f390cd514b7443e2e571f7. Conflicts: test/Transforms/GVN/cond_br2.ll llvm-svn: 194348
* Use type form of getIntPtrType.Matt Arsenault2013-11-103-4/+5
| | | | | | | | This should be inconsequential and is work towards removing the default address space arguments. llvm-svn: 194347
* SimplifyCFG has a heuristics for out-of-order processors that decides when ↵Nadav Rotem2013-11-101-1/+1
| | | | | | | | it is worthwhile to merge branches. It tries to estimate if the operands of the instruction that we want to hoist are ready. This commit marks function arguments as 'ready' because they require no calculation. This boosts libquantum and a few other workloads from the testsuite. llvm-svn: 194346
* Use size function instead of manually calculating it.Matt Arsenault2013-11-101-1/+1
| | | | llvm-svn: 194345
* Teach MergeFunctions about address spacesMatt Arsenault2013-11-101-11/+19
| | | | llvm-svn: 194342
* IR: Refactor GEP range checks, reuse them for other parts of foldingDavid Majnemer2013-11-101-28/+51
| | | | llvm-svn: 194341
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