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* [X86][SSE] Add zero element and general 64-bit VZEXT_LOAD support to ↵Simon Pilgrim2016-01-261-56/+87
| | | | | | | | | | | | | | EltsFromConsecutiveLoads This patch adds support for trailing zero elements to VZEXT_LOAD loads (and checks that no zero elts occur within the consecutive load). It also generalizes the 64-bit VZEXT_LOAD load matching to work for loads other than 2x32-bit loads. After this patch it will also be easier to add support for other basic load patterns like 32-bit VZEXT_LOAD loads, PMOVZX and subvector load insertion. Differential Revision: http://reviews.llvm.org/D16217 llvm-svn: 258798
* [X86] Mark LDS/LES as not being allowed in 64-bit mode.Craig Topper2016-01-261-4/+8
| | | | | | Their opcodes are used as part of the VEX prefix in 64-bit mode. Clearly the disassembler implicitly decoded them as AVX instructions in 64-bit mode, but I think the AsmParser would have encoded them. llvm-svn: 258793
* AMDGPU: Move AMDGPU intrinsics only used by R600Matt Arsenault2016-01-262-10/+13
| | | | llvm-svn: 258790
* AMDGPU: Tidy minor td file issuesMatt Arsenault2016-01-264-247/+249
| | | | | | | | | | Make comments and indentation more consistent. Rearrange a few things to be in a more consistent order, such as organizing subtarget features from those describing an actual device property, and those used as options. llvm-svn: 258789
* AMDGPU: Make v32i8/v64i8 illegal typesMatt Arsenault2016-01-264-21/+13
| | | | | | | | Old intrinsics were forcing these, but they have now all been removed. This fixes large i8 vector operations generally being broken. llvm-svn: 258788
* AMDGPU: Remove old sample intrinsicsMatt Arsenault2016-01-264-61/+0
| | | | | | | | | | | I did my best to try to update all the uses in tests that just happened to use the old ones to the newer intrinsics. I'm not sure I got all of the immediate operand conversions correct, since the value seems to have been ignored by the old pattern but I don't think it really matters. llvm-svn: 258787
* AMDGPU: Add new amdgcn intrinsics for cube instructionsMatt Arsenault2016-01-262-5/+9
| | | | | | | More cleanup to try to get all intrinsics using the correct amdgcn prefix that are as close to the instruction as possible. llvm-svn: 258786
* AMDGPU: Implement read_register and write_register intrinsicsMatt Arsenault2016-01-262-0/+50
| | | | | | | | | | | | | | Some of the special intrinsics now that now correspond to a instruction also have special setting of some registers, e.g. llvm.SI.sendmsg sets m0 as well as use s_sendmsg. Using these explicit register intrinsics may be a better option. Reading the exec mask and others may be useful for debugging. For this I'm not sure this is entirely correct because we would want this to be convergent, although it's possible this is already treated sufficently conservatively. llvm-svn: 258785
* AMDGPU: Restore AMDGPU prefixed rsq intrinsic for nowMatt Arsenault2016-01-264-6/+13
| | | | | | Also move into backend intrinsics to discourage use of the old name. llvm-svn: 258783
* [WebAssembly] Optimize memcpy/memmove/memcpy calls.Dan Gohman2016-01-263-41/+127
| | | | | | | | These calls return their first argument, but because LLVM uses an intrinsic with a void return type, they can't use the returned attribute. Generalize the store results pass to optimize these calls too. llvm-svn: 258781
* [WebAssembly] Remove a completed entry from the README.txt.Dan Gohman2016-01-261-4/+0
| | | | llvm-svn: 258780
* [WebAssembly] Implement unaligned loads and stores.Dan Gohman2016-01-2616-246/+489
| | | | | | Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
* [LIR] Add support for structs and hand unrolled loopsHaicheng Wu2016-01-263-124/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a recommit of r258620 which causes PR26293. The original message: Now LIR can turn following codes into memset: typedef struct foo { int a; int b; } foo_t; void bar(foo_t *f, unsigned n) { for (unsigned i = 0; i < n; ++i) { f[i].a = 0; f[i].b = 0; } } void test(foo_t *f, unsigned n) { for (unsigned i = 0; i < n; i += 2) { f[i] = 0; f[i+1] = 0; } } llvm-svn: 258777
* Use binary search for intrinsic ID lookupsReid Kleckner2016-01-261-14/+60
| | | | | | | | This improves compile time of Function.cpp from 57s to 37s for me locally. Intrinsic IDs are cached on the Function object, so this shouldn't regress performance. llvm-svn: 258774
* LiveIntervalAnalysis: Improve some commentsMatthias Braun2016-01-261-4/+4
| | | | | | As recommended by Justin. llvm-svn: 258771
* Sort intrinsics by LLVM intrinsic name, rather than tablegen def nameReid Kleckner2016-01-261-92/+92
| | | | | | | | | | | | Step one towards using a simple binary search to lookup intrinsic IDs instead of our crazy table generated switch+memcmp+startswith code that makes Function.cpp take about a minute to compile. See PR24785 and PR11951 for why we should do this. The X86 backend contains tables that need to be sorted on intrinsic ID, so reorder those. llvm-svn: 258757
* LiveIntervalAnalysis: Cleanup handleMove{Down|Up}() functions, NFCMatthias Braun2016-01-261-131/+141
| | | | | | | | | | | | | | | | | | | | | | These two functions are hard to reason about. This commit makes the code more comprehensible: - Use four distinct variables (OldIdxIn, OldIdxOut, NewIdxIn, NewIdxOut) with a fixed value instead of a changing iterator I that points to different things during the function. - Remove the early explanation before the function in favor of more detailed comments inside the function. Should have more/clearer comments now stating which conditions are tested and which invariants hold at different points in the functions. The behaviour of the code was not changed. I hope that this will make it easier to review the changes in http://reviews.llvm.org/D9067 which I will adapt next. Differential Revision: http://reviews.llvm.org/D16379 llvm-svn: 258756
* [MC] Use .p2align instead of .alignDan Gohman2016-01-261-5/+2
| | | | | | | | | | | | | | | For historic reasons, the behavior of .align differs between targets. Fortunately, there are alternatives, .p2align and .balign, which make the interpretation of the parameter explicit, and which behave consistently across targets. This patch teaches MC to use .p2align instead of .align, so that people reading code for multiple architectures don't have to remember which way each platform does its .align directive. Differential Revision: http://reviews.llvm.org/D16549 llvm-svn: 258750
* [GVN] Rearrange code to make local vs non-local cases more obvious [NFCI]Philip Reames2016-01-251-13/+18
| | | | llvm-svn: 258747
* [cfi] Cross-DSO CFI diagnostic mode (LLVM part).Evgeniy Stepanov2016-01-251-15/+14
| | | | | | | | * __cfi_check gets a 3rd argument: ubsan handler data * Instead of trapping on failure, call __cfi_check_fail which must be present in the module (generated in the frontend). llvm-svn: 258746
* [GVN] Factor out common code [NFCI]Philip Reames2016-01-251-40/+21
| | | | | | We had the same code duplicated for each type of Def. We also have the entire block duplicated between the local and non-local case, but let's start with local cleanup. llvm-svn: 258740
* X86ISelLowering: Fix cmov(cmov) special lowering bugMatthias Braun2016-01-251-1/+2
| | | | | | | | | | | | | | | | There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) llvm-svn: 258729
* [ThinLTO] Find all needed metadata when linking metadata as postpassTeresa Johnson2016-01-251-6/+27
| | | | | | | | | For metadata postpass linking, after importing all functions, we need to recursively walk through any nodes reached via imported functions to locate needed subprogram metadata. Some might only be reached indirectly via the variable list for an inlined function. llvm-svn: 258728
* [X86][AVX] Add commutation support for VPERM2X128 instructions Simon Pilgrim2016-01-252-0/+16
| | | | | | | | Its main use is to allow memory folding of the 1st operand Differential Revision: http://reviews.llvm.org/D16521 llvm-svn: 258726
* [ThinLTO] Handle DISubprogram reached indirectly from DIImportedEntityTeresa Johnson2016-01-251-2/+4
| | | | | | | Extend fix for PR26037 to identify DISubprogram reached from a DIImportedEntity via a DILexicalBlock. llvm-svn: 258722
* Enable loopreroll to rerool loop with pointer induction variable.Lawrence Hu2016-01-251-50/+123
| | | | | | | | | | | | | | Example: while (buf !=end ) { S += buf[0]; S += buf[1]; buf +=2; }; Differential Revision: http://reviews.llvm.org/D13151 llvm-svn: 258709
* Undo commit 258700 due to missing commit messageLawrence Hu2016-01-251-123/+50
| | | | llvm-svn: 258708
* Reapply commit r25804 with fixMatthew Simpson2016-01-251-11/+226
| | | | | | | | | | | We were hitting an assertion because we were computing smaller type sizes for instructions that cannot be demoted. The fix first determines the instructions that will be demoted, and then applies the smaller type size to only those instructions. This should fix PR26239. llvm-svn: 258705
* Speculatively revert r258620 as it is the likely culprid of PR26293.Quentin Colombet2016-01-253-283/+124
| | | | llvm-svn: 258703
* Temporary disable broken fuzzer/timeout tests.Ivan Krasin2016-01-251-1/+1
| | | | | | | | Reviewers: kcc Differential Revision: http://reviews.llvm.org/D16543 llvm-svn: 258702
* Differential Revision: http://reviews.llvm.org/D13151Lawrence Hu2016-01-251-50/+123
| | | | llvm-svn: 258700
* [WebAssembly] Fix unbalanced register stack code in the case of late DCE.Dan Gohman2016-01-251-3/+3
| | | | | | | Instructions can be DCE'd after the RegStackify pass. If the instruction which would be the pop for what would be a push is removed, don't use a push. llvm-svn: 258694
* [WebAssembly] Minor code formatting cleanups. NFC.Dan Gohman2016-01-253-9/+10
| | | | llvm-svn: 258692
* [SelectionDAG] Use the correct return type for memcpy, memmove, and memset.Dan Gohman2016-01-251-3/+3
| | | | | | | | | | | | | When generating calls to memcpy, memmove, and memset, use void* as the return type rather than void, to match the standard signatures for these functions. This has no practical effect for most targets, since the return values of these calls aren't being used anyway, and most calling conventions tolerate this kind of mismatch. However, this change will help support future optimizations to utilize the return value to avoid holding the argument value live across a call. llvm-svn: 258691
* [DemandedBits] Fix computation of demanded bits for ICmpsJames Molloy2016-01-251-1/+1
| | | | | | | | | | The computation of ICmp demanded bits is independent of the individual operand being evaluated. We simply return a mask consisting of the minimum leading zeroes of both operands. We were incorrectly passing "I" to ComputeKnownBits - this should be "UserI->getOperand(0)". In cases where we were evaluating the 1th operand, we were taking the minimum leading zeroes of it and itself. This should fix PR26266. llvm-svn: 258690
* [AVX512] Adding PTESTNMB/D/W/Q instructionMichael Zuckerman2016-01-251-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D16520 llvm-svn: 258688
* [AVX512] Adding PTESTMB/W/D/Q instruction Michael Zuckerman2016-01-251-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D16519 llvm-svn: 258686
* [ARM] Add DSP build attribute and extension targetingBradley Smith2016-01-252-0/+4
| | | | | | | | This patch was originally committed as r257885, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258683
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-254-7/+112
| | | | | | | | This patch was originally committed as r257884, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258682
* [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-258-1/+95
| | | | | | | | This patch was originally committed as r257883, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258681
* [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned ↵Asaf Badouh2016-01-255-0/+79
| | | | | | | | | | | 52bit integer VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators Differential Revision: http://reviews.llvm.org/D16407 llvm-svn: 258680
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-2512-6/+784
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
* [TableGen] Fix sort order of asm operand classesOliver Stannard2016-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | This is a fix for https://llvm.org/bugs/show_bug.cgi?id=22796. The previous implementation of ClassInfo::operator< allowed cycles of classes such that x < y < z < x, meaning that a list of them cannot be correctly sorted, and the sort order could differ with different standard libraries. The original implementation sorted classes by ValueName if they were otherwise equal. This isn't strictly necessary, but some backends seem to accidentally rely on it. If I reverse this comparison I get 8 test failures spread across the AArch64, Mips and X86 backends, so I have left it in until those backends can be fixed. There was one case in the X86 backend where the observable behaviour of the assembler is changed by this patch. This was because some of the memory asm operands were not marked as children of X86MemAsmOperand. Differential Revision: http://reviews.llvm.org/D16141 llvm-svn: 258677
* Silence a -Wparentheses warning; NFC.Junmo Park2016-01-251-2/+2
| | | | llvm-svn: 258676
* AVX1 : Enable vector masked_load/store to AVX1.Igor Breger2016-01-252-110/+41
| | | | | | | | Use AVX1 FP instructions (vmaskmovps/pd) in place of the AVX2 int instructions (vpmaskmovd/q). Differential Revision: http://reviews.llvm.org/D16528 llvm-svn: 258675
* [AVX512] [CMPPS ][ CMPPD ] Adding full Comparison Predicate names Michael Zuckerman2016-01-251-0/+14
| | | | | | | | | | | X86AsmParser.cpp is missing full comparison predicate names for CMPPD and CMPPS Instructions. X86AsmParser.cpp defines only the short names of the Comparison predicate that you can find in the following pdf: https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Page 5-61 table 5-3 Differential Revision: http://reviews.llvm.org/D16518 llvm-svn: 258671
* [Object][COFF] Revert r258665 - It doesn't do what I had intended.Lang Hames2016-01-251-1/+1
| | | | | | | I'm discussing the right approach for tracking visibility for COFF symbols on the llvm-dev list. llvm-svn: 258666
* [Object][COFF] Set the generic SF_Exported flag on COFF exported symbols.Lang Hames2016-01-241-1/+1
| | | | | | | | | | | | | | The ORC ObjectLinkingLayer uses this flag during symbol lookup. Failure to set it causes all symbols to behave as if they were non-exported, which has caused failures in the kaleidoscope tutorials on Windows. Raising the flag should un-break the tutorials. No test case yet - none of the existing command line tools for printing symbol tables (llvm-nm, llvm-objdump) show the status of this flag, and I don't want to change the format from these tools without consulting their owners. I'll send an email to the dev-list to figure out the right way forward. llvm-svn: 258665
* [COFF] Simplify SetSectionNameDavid Majnemer2016-01-241-12/+10
| | | | | | | | Consolidate the code which handles string table offsets less than 999999 with the code for offsets less than 9999999. While we are here, simplify the code by not using sprintf to generate the string. llvm-svn: 258664
* [LoopSimplify] Reuse changeToUnreachableDavid Majnemer2016-01-241-6/+1
| | | | | | | | | Use existing functionality provided in changeToUnreachable instead of reinventing it in LoopSimplify. No functionality change is intended. llvm-svn: 258663
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