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* Grammar-o.Eric Christopher2012-02-251-1/+1
| | | | llvm-svn: 151418
* Fixed typo.Lang Hames2012-02-251-1/+1
| | | | llvm-svn: 151417
* Add definitions of floating point multiply add/sub and negative multiplyAkira Hatanaka2012-02-253-8/+71
| | | | | | add/sub instructions. llvm-svn: 151415
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-2416-98/+247
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* Remove unused cl::opt, make another opt static.Benjamin Kramer2012-02-242-4/+1
| | | | llvm-svn: 151398
* Add missing staticJakob Stoklund Olesen2012-02-241-3/+3
| | | | llvm-svn: 151396
* Fix undefined behavior.Ahmed Charles2012-02-241-1/+1
| | | | llvm-svn: 151385
* Thumb2 asm aliases for wide bitwise w/ immediate instructions.Jim Grosbach2012-02-241-0/+9
| | | | llvm-svn: 151384
* fix PR12075, a regression in a recent transform I added. In unreachable ↵Chris Lattner2012-02-241-4/+18
| | | | | | code, gep chains can be infinite. Just like "stripPointerCasts", use a set to keep track of visited instructions so we don't recurse infinitely. llvm-svn: 151383
* Add WIN_FTOL_* psudo-instructions to model the unique calling conventionMichael J. Spencer2012-02-245-32/+131
| | | | | | used by the Win32 _ftol2 runtime function. Patch by Joe Groff! llvm-svn: 151382
* Add a -stress-regalloc=<N> option.Jakob Stoklund Olesen2012-02-241-1/+9
| | | | | | | This will limit all register classes to N registers in order to stress test register allocation. llvm-svn: 151379
* X11/X2 loads around indirect calls on ppc64 should not be deleted.Hal Finkel2012-02-241-2/+4
| | | | llvm-svn: 151374
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+3
| | | | | | | This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. llvm-svn: 151373
* Teach GVN that x+y is the same as y+x and that x<y is the same as y>x.Duncan Sands2012-02-241-1/+16
| | | | llvm-svn: 151365
* SDAGBuilder: Remove register sets that were never read and prune dead code ↵Benjamin Kramer2012-02-241-63/+3
| | | | | | surrounding it. llvm-svn: 151364
* Remove dead code.Richard Osborne2012-02-241-3/+1
| | | | | | Patch by Ahmed Charles llvm-svn: 151360
* Workaround a miscompilation by gcc-4.3 that showed up as a failureDuncan Sands2012-02-241-1/+1
| | | | | | of the StringRef.Split2 unittest on 32 bit machines. llvm-svn: 151358
* ScheduleDAGInstrs.h:155: warning: suggest parentheses around `&&' within `||'.Nick Lewycky2012-02-241-1/+1
| | | | llvm-svn: 151355
* PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick2012-02-242-35/+80
| | | | llvm-svn: 151348
* ARM Thumb symbol references in assembly need the low bit set.Jim Grosbach2012-02-241-0/+5
| | | | | | | | | Add support for a missed case when the symbols in a difference expression are in the same section but not the same fragment. rdar://10924681 llvm-svn: 151345
* Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove ↵Pete Cooper2012-02-242-9/+15
| | | | | | duplicate patterns for selecting the intrinsics llvm-svn: 151342
* comment fixJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151341
* some comment fixJia Liu2012-02-241-3/+3
| | | | llvm-svn: 151340
* comment fixJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151339
* replace a balnk with -Jia Liu2012-02-241-1/+1
| | | | llvm-svn: 151337
* If the Address of a variable is an argument then treat the entireEric Christopher2012-02-241-3/+7
| | | | | | | | | | | variable declaration as an argument because we want that address anyhow for our debug information. This seems to fix rdar://9965111, at least we have more debug information than before and from reading the assembly it appears to be the correct location. llvm-svn: 151335
* Tabs, formatting and long lines oh my!Eric Christopher2012-02-241-4/+6
| | | | llvm-svn: 151334
* 80 columns of Mips InstPrinter MakefileJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151332
* Switch ARM target to register masks.Jakob Stoklund Olesen2012-02-245-35/+25
| | | | | | | | | | | | | I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
* Make sure the regs are low regs for tMUL size reduction.Jim Grosbach2012-02-241-1/+6
| | | | llvm-svn: 151318
* Thumb2 size reduction fix for tied operands of tMUL.Jim Grosbach2012-02-241-1/+13
| | | | | | | | | The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. llvm-svn: 151315
* EE/Interpreter/ExternalFunctions.cpp: Staticize lle_X_() entries. They can ↵NAKAMURA Takumi2012-02-241-0/+8
| | | | | | be mapped in FuncNames[] at the initialization. llvm-svn: 151313
* EE/Interpreter/ExternalFunctions.cpp: Prune "C" linkage to suppress warnings ↵NAKAMURA Takumi2012-02-241-22/+0
| | | | | | | | | | | | with -Wreturn-type (and MSC's w4190). In historical reason, Interpreter's external entries had prefix "lle_X_" as C linkage, even for well-known entries in EE/Interpreter. Now, at least on ToT, they are resolved via FuncNames[] mapper. We will not need their symbols are expected to be exported any more. Clang r150128 has introduced the warning <"%0 has C-linkage specified, but returns user-defined type %1 which is incompatible with C">. llvm-svn: 151312
* When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman2012-02-241-0/+5
| | | | | | | bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. llvm-svn: 151310
* Allow an integer to be converted into an MMX type when it's used in an inlineBill Wendling2012-02-231-2/+8
| | | | | | | asm. <rdar://problem/10106006> llvm-svn: 151303
* Emit global ctors into .CRT$XCU instead of .ctors on Win32. Patch by Joe Groff!Michael J. Spencer2012-02-231-6/+16
| | | | llvm-svn: 151289
* Bump SmallString to the minimum required amount for raw_ostream to avoid ↵Benjamin Kramer2012-02-231-2/+2
| | | | | | | | allocation. It's is a bit annoying, we should hide this implementation detail better. llvm-svn: 151284
* MCize function entry label emission on PowerPC64 properly.Roman Divacky2012-02-231-6/+14
| | | | llvm-svn: 151278
* BitVectorize loop.Benjamin Kramer2012-02-231-3/+1
| | | | llvm-svn: 151274
* post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored ↵Benjamin Kramer2012-02-231-28/+22
| | | | | | | | two meaningful states. Rename it to LiveRegs to make it more clear what's stored inside. llvm-svn: 151273
* post-ra-sched: Replace a std::set of regs with a bitvector.Benjamin Kramer2012-02-231-5/+4
| | | | | | | | | Assuming that a single std::set node adds 3 control words, a bitvector can store (3*8+4)*8=224 registers in the allocated memory of a single element in the std::set (x86_64). Also we don't have to call malloc for every register added. llvm-svn: 151269
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-237-63/+240
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Fix the numbering of some of the registers and reclassify a couple of them.Brendon Cahoon2012-02-231-66/+64
| | | | | | Also, some basic clean up. Patch by Evandro Menezes. llvm-svn: 151266
* Make calls scheduling boundaries post-ra.Jakob Stoklund Olesen2012-02-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before register allocation, instructions can be moved across calls in order to reduce register pressure. After register allocation, we don't gain a lot by moving callee-saved defs across calls. In fact, since the scheduler doesn't have a good idea how registers are used in the callee, it can't really make good scheduling decisions. This changes the schedule in two ways: 1. Latencies to call uses and defs are no longer accounted for, causing some random shuffling around calls. This isn't really a problem since those uses and defs are inaccurate proxies for what happens inside the callee. They don't represent registers used by the call instruction itself. 2. Instructions are no longer moved across calls. This didn't happen very often, and the scheduling decision was made on dubious information anyway. As with any scheduling change, benchmark numbers shift around a bit, but there is no positive or negative trend from this change. This makes the post-ra scheduler 5% faster for ARM targets. The secret motivation for this patch is the introduction of register mask operands representing call clobbers. The most efficient way of handling regmasks in ScheduleDAGInstrs is to model them as barriers for physreg live ranges, but not for virtreg live ranges. That's fine pre-ra, but post-ra it would have the same effect as this patch. llvm-svn: 151265
* Reflow code, no functionality change.Benjamin Kramer2012-02-231-17/+12
| | | | llvm-svn: 151262
* Strip a layer of boilerplate from the VLIWPacketizer by storing the ↵Benjamin Kramer2012-02-231-18/+8
| | | | | | scheduler as an opaque pointer. llvm-svn: 151252
* Remove unused variable.Duncan Sands2012-02-231-1/+0
| | | | llvm-svn: 151251
* Fix to make sure that a comdat group gets generated correctly for a static ↵Anton Korobeynikov2012-02-231-1/+2
| | | | | | | | | | member of instantiated C++ templates. Patch by Kristof Beyls! llvm-svn: 151250
* Update for the removal of Hashing.cpp.Jay Foad2012-02-231-1/+0
| | | | llvm-svn: 151249
* Reinstate r151049 now that GeneralHash is fixed.Jay Foad2012-02-232-34/+131
| | | | llvm-svn: 151248
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