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* Change C++ style comments to C style comments in X86 disassembler. Patch ↵Craig Topper2011-10-051-2/+2
| | | | | | from Joe Abbey. llvm-svn: 141162
* Avoid exponential recursion in SCEV getConstantEvolvingPHI and ↵Andrew Trick2011-10-051-34/+82
| | | | | | | | | | EvaluateExpression. Note to compiler writers: never recurse on multiple instruction operands without memoization. Fixes rdar://10187945. Was taking 45s, now taking 5ms. llvm-svn: 141161
* Insert space.Akira Hatanaka2011-10-051-1/+1
| | | | llvm-svn: 141158
* Do not examine variadic or implicit operands if instruction is a return (jr).Akira Hatanaka2011-10-051-2/+3
| | | | llvm-svn: 141157
* Clean up function Filler::delayHasHazard. Akira Hatanaka2011-10-051-4/+6
| | | | llvm-svn: 141156
* Remove function Filler::insertCallUses.Akira Hatanaka2011-10-051-29/+14
| | | | | | Record the registers used and defined by a call in Filler::insertDefsUses. llvm-svn: 141154
* Clean up Filler::findDelayInstr.Akira Hatanaka2011-10-051-15/+10
| | | | llvm-svn: 141152
* Remove function Filler::isDelayFiller. Check if I is the same instruction thatAkira Hatanaka2011-10-051-11/+7
| | | | | | filled the last delay slot visited. llvm-svn: 141151
* Clean up Filler::runOnMachineBasicBlock. Change interface ofAkira Hatanaka2011-10-051-17/+20
| | | | | | Filler::findDelayInstr. llvm-svn: 141150
* Define a statistic for the number of slots that were filled with useful Akira Hatanaka2011-10-051-0/+2
| | | | | | instructions (instructions that are not NOP). llvm-svn: 141149
* Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true beforeAkira Hatanaka2011-10-051-1/+0
| | | | | | I->getDesc().hasDelaySlot() does. llvm-svn: 141148
* Add comments and move assignment statement. If sawStore is true, sawLoad doesAkira Hatanaka2011-10-051-1/+3
| | | | | | not have to be set. llvm-svn: 141147
* Correct description string of enable-mips-delay-filler.Akira Hatanaka2011-10-051-1/+1
| | | | llvm-svn: 141146
* Look at the number of entries in the jump table and jump to a 'trap' block ifBill Wendling2011-10-051-14/+50
| | | | | | the value exceeds that number. llvm-svn: 141143
* Checkpoint for SJLJ EH code.Bill Wendling2011-10-051-3/+75
| | | | | | | This is a first pass at generating the jump table for the sjlj dispatch. It currently generates something plausible, but hasn't been tested thoroughly. llvm-svn: 141140
* Also add <imp-use,kill> flags for redefined super-registers.Jakob Stoklund Olesen2011-10-051-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 is rewritten as: %D2<def> = COPY %D0, %Q1<imp-def> %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def> The first COPY doesn't care about the previous value of %Q1, so it doesn't read that register. The second COPY is a partial redefinition of %Q1, so it implicitly kills and redefines that register. This makes it possible to recognize instructions that can harmlessly clobber the full super-register. The write and don't read the super-register. llvm-svn: 141139
* Also add <def,undef> flags when coalescing sub-registers.Jakob Stoklund Olesen2011-10-051-0/+8
| | | | | | | | RegisterCoalescer can create sub-register defs when it is joining a register with a sub-register. Add <undef> flags to these new sub-register defs where appropriate. llvm-svn: 141138
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-047-4/+136
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. llvm-svn: 141135
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-046-7/+230
| | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
* Create a mapping between the landing pad basic block and the call site index ↵Bill Wendling2011-10-042-0/+5
| | | | | | for later use. llvm-svn: 141125
* Allow <undef> flags on def operands as well as uses.Jakob Stoklund Olesen2011-10-041-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <undef> flag says that a MachineOperand doesn't read its register, or doesn't depend on the previous value of its register. A full register def never depends on the previous register value. A partial register def may depend on the previous value if it is intended to update part of a register. For example: %vreg10:dsub_0<def,undef> = COPY %vreg1 %vreg10:dsub_1<def> = COPY %vreg2 The first copy instruction defines the full %vreg10 register with the bits not covered by dsub_0 defined as <undef>. It is not considered a read of %vreg10. The second copy modifies part of %vreg10 while preserving the rest. It has an implicit read of %vreg10. This patch adds a MachineOperand::readsReg() method to determine if an operand reads its register. Previously, this was modelled by adding a full-register <imp-def> operand to the instruction. This approach makes it possible to determine directly from a MachineOperand if it reads its register. No scanning of MI operands is required. llvm-svn: 141124
* Replace snprintf with raw_string_ostream.Francois Pichet2011-10-041-7/+4
| | | | llvm-svn: 141116
* Allow Operator ArgumentsDavid Greene2011-10-041-5/+13
| | | | | | | | | | | | | | | When resolving an operator list element reference, resolve all operator operands and try to fold the operator first. This allows the operator to collapse to a list which may then be indexed. Before, it was not possible to do this: class D<int a, int b> { ... } class C<list<int> A> : D<A[0], A[1]>; class B<list<int> b> : C<!foreach(...,b)>; Now it is. llvm-svn: 141101
* Unbreak CMake build.Ted Kremenek2011-10-041-1/+2
| | | | llvm-svn: 141097
* Put GCOVFile and other related interface in a common header so that llvm-cov ↵Devang Patel2011-10-041-0/+281
| | | | | | tool can share it with GCOV writer. llvm-svn: 141095
* Unbreak MSVC build.Francois Pichet2011-10-041-0/+4
| | | | llvm-svn: 141093
* Teach PPCInstrInfo to handle sub-classes.Jakob Stoklund Olesen2011-10-041-14/+14
| | | | | | This has already been done for most other targets. llvm-svn: 141083
* tblgen: add preprocessor as a separate modeChe-Liang Chiou2011-10-044-0/+679
| | | | | | | | | | | | | | This patch adds a preprocessor that can expand nested for-loops for saving some copy-n-paste in *.td files. The preprocessor is not yet integrated with TGParser, and so it has no direct effect on *.td inputs. However, you may preprocess an td input (and only preprocess it). To test the proprecessor, type: tblgen -E -o $@ $< llvm-svn: 141079
* Set operation actions to legal types only.Nadav Rotem2011-10-041-8/+9
| | | | llvm-svn: 141075
* Operations should be custom lowered only if their type is legal.Nadav Rotem2011-10-041-6/+8
| | | | | Test: CellSPU/v2i32.ll when running with -promote-elements llvm-svn: 141074
* The product of two chrec's can always be represented as a chrec.Nick Lewycky2011-10-041-32/+72
| | | | llvm-svn: 141066
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-045-57/+105
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* LSR should avoid redundant edge splitting.Andrew Trick2011-10-042-3/+6
| | | | | | | | This handles the case in which LSR rewrites an IV user that is a phi and splits critical edges originating from a switch. Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely" llvm-svn: 141059
* whitespaceAndrew Trick2011-10-041-18/+18
| | | | llvm-svn: 141058
* Remove last references to hotpatch.Rafael Espindola2011-10-042-2/+0
| | | | llvm-svn: 141057
* Generic cleanup.Bill Wendling2011-10-041-23/+16
| | | | llvm-svn: 141050
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-032-0/+84
| | | | llvm-svn: 141046
* Tidy up. 80 columns.Jim Grosbach2011-10-031-1/+1
| | | | llvm-svn: 141043
* Use the PC label ID rather than '1'. Add support for thumb-2, because I ↵Bill Wendling2011-10-031-10/+41
| | | | | | heard that some people use it. llvm-svn: 141042
* Don't carry over the dispatchsetup hack from the old system.Bill Wendling2011-10-031-7/+1
| | | | llvm-svn: 141040
* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-031-0/+11
| | | | llvm-svn: 141038
* Fix typo in comments.Nick Lewycky2011-10-031-2/+2
| | | | llvm-svn: 141032
* Check-pointing the new SjLj EH lowering.Bill Wendling2011-10-032-0/+77
| | | | | | | | | | | This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. llvm-svn: 141031
* Add support for 64-bit logical NOR.Akira Hatanaka2011-10-031-0/+7
| | | | llvm-svn: 141029
* Add support for 64-bit count leading ones and zeros instructions.Akira Hatanaka2011-10-031-0/+15
| | | | llvm-svn: 141028
* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-031-31/+33
| | | | | | the need for returning a std::pair. llvm-svn: 141026
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-033-0/+18
| | | | llvm-svn: 141025
* Add support for 64-bit divide instructions.Akira Hatanaka2011-10-033-3/+17
| | | | llvm-svn: 141024
* Add C api for Instruction->eraseFromParent().Devang Patel2011-10-031-0/+4
| | | | llvm-svn: 141023
* Thumb2 ADD/SUB can take SP as a destination register.Jim Grosbach2011-10-031-18/+18
| | | | | | | It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. llvm-svn: 141020
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