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* Debug info: When updating debug info during SROA, do not emit debug infoAdrian Prantl2015-02-091-8/+18
| | | | | | | | | | for any padding introduced by SROA. In particular, do not emit debug info for an alloca that represents only the padding introduced by a previous iteration. Fixes PR22495. llvm-svn: 228632
* Debug info: Use DW_OP_bit_piece instead of DW_OP_piece in theAdrian Prantl2015-02-097-49/+46
| | | | | | | | | | | intermediate representation. This - increases consistency by using the same granularity everywhere - allows for pieces < 1 byte - DW_OP_piece didn't actually allow storing an offset. Part of PR22495. llvm-svn: 228631
* [Hexagon] Adding missing load instructions and removing an unused multiclass ↵Colin LeMahieu2015-02-091-38/+169
| | | | | | parameter. llvm-svn: 228630
* [Hexagon] Factoring classes out of some load patterns and deleting some ↵Colin LeMahieu2015-02-091-40/+87
| | | | | | unused ones. llvm-svn: 228627
* [Statepoint] Improve two asserts, fix some style (NFC)Ramkumar Ramachandra2015-02-092-5/+6
| | | | | | | | | | | | | | | Summary: It's important that our users immediately know what gc.safepoint_poll is. Also fix the style of the declaration of CreateGCStatepoint, in preparation for another change that will wrap it. Reviewers: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7517 llvm-svn: 228626
* PlaceSafepoints: modernize gc.result.* -> gc.resultRamkumar Ramachandra2015-02-091-12/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D7516 llvm-svn: 228625
* DebugInfo: Remove DW_TAG_constantDuncan P. N. Exon Smith2015-02-092-3/+1
| | | | | | | | Remove handling for DW_TAG_constant. We started producing it in r110656, but reverted that in r110876 without dropping the support. Finish the job. llvm-svn: 228623
* Update file comment to clarify points highlighted in review (NFC)Philip Reames2015-02-091-31/+30
| | | | llvm-svn: 228621
* Use range for loops in PlaceSafepoints (NFC)Philip Reames2015-02-091-8/+4
| | | | llvm-svn: 228620
* IR: Take uint64_t in DIBuilder::createExpression()Duncan P. N. Exon Smith2015-02-092-4/+10
| | | | | | | | | | | `DIExpression` deals with `uint64_t`, so it doesn't make sense that `createExpression()` is created from `int64_t`. Switch to `uint64_t` to unify them. I've temporarily left in the `int64_t` version, which forwards to the `uint64_t` version. I'll delete it once I've updated the callers. llvm-svn: 228619
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-0912-470/+226
| | | | llvm-svn: 228614
* MemDerefPrinter: Require DataLayoutPass for higher accuracyRamkumar Ramachandra2015-02-091-3/+12
| | | | | | | | | | Without a valid data layout, deferenceable(N) doesn't get parsed or propagated. Since this is the key item we are testing, add a dependency on the pass. Differential Revision: http://reviews.llvm.org/D7508 llvm-svn: 228611
* Add basic tests for PlaceSafepointsPhilip Reames2015-02-091-5/+21
| | | | | | This is just adding really simple tests which should have been part of the original submission. When doing so, I discovered that I'd mistakenly removed required pieces when preparing the patch for upstream submission. I fixed two such bugs in this submission. llvm-svn: 228610
* Verifier: Const-qualify Metadata, NFCDuncan P. N. Exon Smith2015-02-091-7/+7
| | | | llvm-svn: 228609
* isDereferenceablePointer: look through gc.relocate callsRamkumar Ramachandra2015-02-091-0/+9
| | | | | | | | | | While a theoretical GC might change dereferenceability on collection, there is no such known collector and no need to account for the case with a flag yet. Differential Revision: http://reviews.llvm.org/D7454 llvm-svn: 228606
* [Hexagon] Removing v2-4 flags. V4 is the minimum supported version.Colin LeMahieu2015-02-094-93/+64
| | | | llvm-svn: 228605
* Reduce the LockFileManager timeout, and provide unsafeRemoveLockFileBen Langmuir2015-02-091-2/+6
| | | | | | | | | | 5 minutes is an eternity, so try to strike a better balance between waiting long enough for any reasonable module build and not so long that users kill the process because they think it's hanging. Also give the client a way to delete the lock file after a timeout. llvm-svn: 228603
* [Hexagon] Factoring classes out of store patterns.Colin LeMahieu2015-02-091-34/+47
| | | | llvm-svn: 228602
* [Hexagon] Formatting v5 TD file. Removing commented defs.Colin LeMahieu2015-02-091-38/+28
| | | | llvm-svn: 228598
* MemDepPrinter: cleanup a few loops (NFC)Ramkumar Ramachandra2015-02-091-9/+8
| | | | | | | | | Make use of the newly introduced inst_range to clean up two loops. Clean up a third one while at it. Differential Revision: http://reviews.llvm.org/D7455 llvm-svn: 228596
* [Hexagon] Cleaning up definition formatting.Colin LeMahieu2015-02-091-85/+85
| | | | llvm-svn: 228593
* Bugfix: SCEV incorrectly marks certain add recurrences as nswSanjoy Das2015-02-091-2/+10
| | | | | | | | | | | | | | When creating a scev for sext({X,+,Y}), scev checks if the expression is equivalent to {sext X,+,zext Y}. If it can prove that, it also tags the original {X,+,Y} as <nsw>, which is not correct. In the test case I run `-scalar-evolution` twice because the bug manifests only once SCEV has run through and seen the `sext` expressions (and then does a in-place mutation on {X,+,Y}). Differential Revision: http://reviews.llvm.org/D7495 llvm-svn: 228586
* This change implements the following three logical vector operations:Kit Barton2015-02-091-0/+25
| | | | | | | | | | | | veqv (vector equivalence) vnand vorc I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions. Phabricator review: http://reviews.llvm.org/D7469 llvm-svn: 228580
* rename variable to give it some meaning; remove obvious comments; NFCSanjay Patel2015-02-091-12/+12
| | | | llvm-svn: 228579
* fix comment that didn't match the code; remove unnecessary braces; NFCSanjay Patel2015-02-091-4/+3
| | | | llvm-svn: 228578
* Allow ScalarEvolution to catch more min/max casesJohannes Doerfert2015-02-091-23/+25
| | | | | | | | | | | | For the attached test case different types are used in the ICmpInst and SelectInst that represent the min/max expressions. However, if the ICmpInst type is smaller a comparison with the sign/zero extended operands would have yielded the same result. This situation might arise after the instruction combination pass was applied. Differential Revision: http://reviews.llvm.org/D7338 llvm-svn: 228572
* Fix a bug in DemoteRegToStack where a reload instruction was inserted into theAkira Hatanaka2015-02-091-18/+16
| | | | | | | | | | | | | | | | | | wrong basic block. This would happen when the result of an invoke was used by a phi instruction in the invoke's normal destination block. An instruction to reload the invoke's value would get inserted before the critical edge was split and a new basic block (which is the correct insertion point for the reload) was created. This commit fixes the bug by splitting the critical edge before all the reload instructions are inserted. Also, hoist up the code which computes the insertion point to the only place that need that computation. rdar://problem/15978721 llvm-svn: 228566
* MC: Calculate intra-section symbol differences correctly for COFFDavid Majnemer2015-02-091-6/+11
| | | | | | This fixes PR22060. llvm-svn: 228565
* [X86] Remove 256-bit and 512-bit memop pattern fragments. They are no longer ↵Craig Topper2015-02-092-14/+2
| | | | | | used. llvm-svn: 228563
* [X86] Remove 'memop' uses from AVX512. Use 'load' instead.Craig Topper2015-02-091-81/+71
| | | | llvm-svn: 228562
* DeadArgElim: fix mismatch in accounting of array return types.Tim Northover2015-02-091-39/+47
| | | | | | | | | | | | Some parts of DeadArgElim were only considering the individual fields of StructTypes separately, but others (where insertvalue & extractvalue instructions occur) also looked into ArrayTypes. This one is an actual bug; the mismatch can lead to an argument being considered used by a return sub-value that isn't being tracked (and hence is dead by default). It then gets incorrectly eliminated. llvm-svn: 228559
* DeadArgElim: assess uses of entire return value aggregate.Tim Northover2015-02-091-26/+26
| | | | | | | | | | | | | | | | | | | | | | | Previously, a non-extractvalue use of an aggregate return value meant the entire return was considered live (the algorithm gave up entirely). This was correct, but conservative. It's better to actually look at that Use, making the analysis results apply to all sub-values under consideration. E.g. %val = call { i32, i32 } @whatever() [...] ret { i32, i32 } %val The return is using the entire aggregate (sub-values 0 and 1). We can still simplify @whatever if we can prove that this return is itself unused. Also unifies the logic slightly between aggregate and non-aggregate cases.. llvm-svn: 228558
* [Orc] Add a JITSymbol class to the Orc APIs, refactor APIs, update clients.Lang Hames2015-02-091-2/+2
| | | | | | | | | | | | | | | | This patch refactors a key piece of the Orc APIs: It removes the *::getSymbolAddress and *::lookupSymbolAddressIn methods, which returned target addresses (uint64_ts), and replaces them with *::findSymbol and *::findSymbolIn respectively, which return instances of the new JITSymbol type. Unlike the old methods, calling findSymbol or findSymbolIn does not cause the symbol to be immediately materialized when found. Instead, the symbol will be materialized if/when the getAddress method is called on the returned JITSymbol. This allows us to query for the existence of symbols without actually materializing them. In the future I expect more information to be attached to the JITSymbol class, for example whether the returned symbol is a weak or strong definition. This will allow us to properly handle weak symbols and multiple definitions. llvm-svn: 228557
* InstCombine: propagate nonNull through assumeRamkumar Ramachandra2015-02-091-1/+8
| | | | | | | | | Make assume (load (call|invoke) != null) set nonNull return attribute for the call and invoke. Also include tests. Differential Revision: http://reviews.llvm.org/D7107 llvm-svn: 228556
* Fix -Wuninitialized build by referencing the relevant ctor parameter instead ↵David Blaikie2015-02-088-8/+8
| | | | | | of the base class member variable. llvm-svn: 228554
* Make PDBSymbol's IPDBSymbol reference const.Zachary Turner2015-02-0832-33/+33
| | | | llvm-svn: 228553
* Bugfix: ScalarEvolution incorrectly assumes that the start of certainSanjoy Das2015-02-081-1/+18
| | | | | | | | | | | | | add recurrences don't overflow. This change makes the optimization more restrictive. It still assumes that an overflowing `add nsw` is undefined behavior; and this change will need revisiting once we have a consistent semantics for poison values. Differential Revision: http://reviews.llvm.org/D7331 llvm-svn: 228552
* [X86] Remove the remaining uses of memop from AVX and AVX2 instruction ↵Craig Topper2015-02-082-237/+211
| | | | | | patterns. AVX and AVX2 can handle unaligned loads being folded so we can just use 'load' llvm-svn: 228551
* Metadata: Use <algorithm> to simplify code. NFC.Benjamin Kramer2015-02-081-30/+12
| | | | llvm-svn: 228550
* DebugInfoPDB: Make the symbol base case hold an IPDBSession ref.Zachary Turner2015-02-0832-67/+87
| | | | | | | | | Dumping a symbol often requires access to data that isn't inside the symbol hierarchy, but which is only accessible through the top-level session. This patch is a pure interface change to give symbols a reference to the session. llvm-svn: 228542
* fix typos; NFCSanjay Patel2015-02-081-3/+3
| | | | llvm-svn: 228529
* Make UTF8->UTF16 conversion null terminate output on empty input.Zachary Turner2015-02-081-1/+4
| | | | llvm-svn: 228527
* Moved AVX2 vbroadcast (reg) instruction foldings under the correct grouping. ↵Simon Pilgrim2015-02-081-3/+3
| | | | | | NFC. llvm-svn: 228526
* Correctly combine alias.scope metadata by a union instead of intersectingBjorn Steinbrink2015-02-084-2/+28
| | | | | | | | | | | | | | | | | Summary: The alias.scope metadata represents sets of things an instruction might alias with. When generically combining the metadata from two instructions the result must be the union of the original sets, because the new instruction might alias with anything any of the original instructions aliased with. Reviewers: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7490 llvm-svn: 228525
* Masked Gather and Scatter Intrinsics.Elena Demikhovsky2015-02-082-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gather and Scatter are new introduced intrinsics, comming after recently implemented masked load and store. This is the first patch for Gather and Scatter intrinsics. It includes only the syntax, parsing and verification. Gather and Scatter intrinsics allow to perform multiple memory accesses (read/write) in one vector instruction. The intrinsics are not target specific and will have the following syntax: Gather: declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> <vector of ptrs>, i32 <alignment>, <16 x i1> <mask>, <16 x i32> <passthru>) declare <8 x float> @llvm.masked.gather.v8f32(<8 x float*><vector of ptrs>, i32 <alignment>, <8 x i1> <mask>, <8 x float><passthru>) Scatter: declare void @llvm.masked.scatter.v8i32(<8 x i32><vector value to be stored> , <8 x i32*><vector of ptrs> , i32 <alignment>, <8 x i1> <mask>) declare void @llvm.masked.scatter.v16i32(<16 x i32> <vector value to be stored> , <16 x i32*> <vector of ptrs>, i32 <alignment>, <16 x i1><mask> ) Vector of ptrs - a set of source/destination addresses, to load/store the value. Mask - switches on/off vector lanes to prevent memory access for switched-off lanes vector of ptrs, value and mask should have the same vector width. These are code examples where gather / scatter should be used and will allow function vectorization ;void foo1(int * restrict A, int * restrict B, int * restrict C) { ; for (int i=0; i<SIZE; i++) { ; A[i] = B[C[i]]; ; } ;} ;void foo3(int * restrict A, int * restrict B) { ; for (int i=0; i<SIZE; i++) { ; A[B[i]] = i+5; ; } ;} Tests will come in the following patches, with CodeGen and Vectorizer. http://reviews.llvm.org/D7433 llvm-svn: 228521
* ARM & AArch64: teach LowerVSETCC that output type size may differ from input.Tim Northover2015-02-082-18/+27
| | | | | | | | | | | | | | | | | | While various DAG combines try to guarantee that a vector SETCC operation will have the same output size as input, there's nothing intrinsic to either creation or LegalizeTypes that actually guarantees it, so the function needs to be ready to handle a mismatch. Fortunately this is easy enough, just extend or truncate the naturally compared result. I couldn't reproduce the failure in other backends that I know have SIMD, so it's probably only an issue for these two due to shared heritage. Should fix PR21645. llvm-svn: 228518
* Removed unused function mistakenly left in, triggering -Werror.Zachary Turner2015-02-081-21/+0
| | | | llvm-svn: 228517
* Some cleanup for libpdb.Zachary Turner2015-02-0833-71/+663
| | | | | | | | | | | This patch implements a few of the optional suggestions from the initial patch comitting libpdb. In particular, it implements a virtual function out of line for each of the concrete classes. A few other minor cleanups exist as well, such as using override instead of virtual, etc. llvm-svn: 228516
* [X86] Add register use/def for wrmsr and rdmsr.Craig Topper2015-02-071-0/+2
| | | | llvm-svn: 228515
* [X86] Add GETSEC instruction.Craig Topper2015-02-071-0/+6
| | | | llvm-svn: 228514
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