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* [PGO] Fix some style issue of ControlHeightReductionFangrui Song2018-09-071-33/+30
| | | | | | | | | | | | Reviewers: yamauchi Reviewed By: yamauchi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51811 llvm-svn: 341702
* [X86] Modify the the rdtscp intrinsic to return values instead of taking a ↵Craig Topper2018-09-072-18/+55
| | | | | | | | | | pointer argument Similar to what was recently done for addcarry/subborrow and has been done for rdrand/rdseed for a while. It's better to use two results and an explicit store in IR when the store isn't part of the semantics of the instruction. This allows store->load forwarding to happen in the middle end. Or the store to be removed if its never loaded. Differential Revision: https://reviews.llvm.org/D51803 llvm-svn: 341698
* [PGO][CHR] Build/warning fixHiroshi Yamauchi2018-09-071-0/+2
| | | | llvm-svn: 341692
* [RISCV] Fix crash in decoding instruction with unknown floating point ↵Ana Pazos2018-09-073-1/+28
| | | | | | | | | | | | | | | | | | | | rounding mode Summary: Instead of crashing in printFRMArg, decode and warn about invalid instruction. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51705 llvm-svn: 341691
* [RISCV] Fix AddressSanitizer heap-buffer-overflow in disassemblingAna Pazos2018-09-071-0/+8
| | | | | | | | | | | | | | | | | | Summary: RISCVDisassembler should check number of bytes available before reading them. Crash noticed when enabling -DLLVM_USE_SANITIZER=Address. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51708 llvm-svn: 341686
* NFC: remove magic bool in LoopIdiomRecognizeJF Bastien2018-09-071-9/+9
| | | | | | Use an enum class instead. llvm-svn: 341684
* [PGO][CHR] Small cleanup.Hiroshi Yamauchi2018-09-071-36/+17
| | | | | | | | | | | | | | | | Summary: Do away with demangling. It wasn't really necessary. Declared some local functions to be static. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51740 llvm-svn: 341681
* [X86] Change the addcarry and subborrow intrinsics to return 2 results and ↵Craig Topper2018-09-073-22/+76
| | | | | | | | | | remove the pointer argument. We should represent the store directly in IR instead. This gives the middle end a chance to remove it if it can see a load from the same address. Differential Revision: https://reviews.llvm.org/D51769 llvm-svn: 341677
* [X86] Teach X86DAGToDAGISel::foldLoadStoreIntoMemOperand to handle loads in ↵Craig Topper2018-09-071-7/+21
| | | | | | | | | | operand 1 of commutable operations. Previously we only handled loads in operand 0, but nothing guarantees the load will be operand 0 for commutable operations. Differential Revision: https://reviews.llvm.org/D51768 llvm-svn: 341675
* [InstCombine] Fold (min/max ~X, Y) -> ~(max/min X, ~Y) when Y is freely ↵Craig Topper2018-09-072-13/+46
| | | | | | | | | | | | invertible If the ~X wasn't able to simplify above the max/min, we might be able to simplify it by moving it below the max/min. I had to modify the ~(min/max ~X, Y) transform to prevent getting stuck in a loop when we saw the new ~(max/min X, ~Y) before the ~Y had been folded away to remove the new not. Differential Revision: https://reviews.llvm.org/D51398 llvm-svn: 341674
* [LV] Fix code gen for conditionally executed loads and storesAnna Thomas2018-09-071-8/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a latent bug in loop vectorizer which generates incorrect code for memory accesses that are executed conditionally. As pointed in review, this bug definitely affects uniform loads and may affect conditional stores that should have turned into scatters as well). The code gen for conditionally executed uniform loads on architectures that support masked gather instructions is broken. Without this patch, we were unconditionally executing the *conditional* load in the vectorized version. This patch does the following: 1. Uniform conditional loads on architectures with gather support will have correct code generated. In particular, the cost model (setCostBasedWideningDecision) is fixed. 2. For the recipes which are handled after the widening decision is set, we use the isScalarWithPredication(I, VF) form which is added in the patch. 3. Fix the vectorization cost model for scalarization (getMemInstScalarizationCost): implement and use isPredicatedInst to identify *all* predicated instructions, not just scalar+predicated. So, now the cost for scalarization will be increased for maskedloads/stores and gather/scatter operations. In short, we should be choosing the gather/scatter in place of scalarization on archs where it is profitable. 4. We needed to weaken the assert in useEmulatedMaskMemRefHack. Reviewers: Ayal, hsaito, mkuper Differential Revision: https://reviews.llvm.org/D51313 llvm-svn: 341673
* Hot cold splitting passAditya Kumar2018-09-074-0/+379
| | | | | | | | | | | | Find cold blocks based on profile information (or optionally with static analysis). Forward propagate profile information to all cold-blocks. Outline a cold region. Set calling conv and prof hint for the callsite of the outlined function. Worked in collaboration with: Sebastian Pop <s.pop@samsung.com> Differential Revision: https://reviews.llvm.org/D50658 llvm-svn: 341669
* [InstCombine] Do not fold scalar ops over select with vector condition.Florian Hahn2018-09-071-0/+8
| | | | | | | | | | | | | If OtherOpT or OtherOpF have scalar types and the condition is a vector, we would create an invalid select. Reviewers: spatel, john.brawn, mssimpso, craig.topper Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D51781 llvm-svn: 341666
* [DebugInfo] Handle stack slot offsets for spilled sub-registers in LDVDavid Stenberg2018-09-071-30/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Extend LDV so that stack slot offsets for spilled sub-registers are added to the emitted debug locations. This is accomplished by querying InstrInfo::getStackSlotRange(). With this change, LDV will add a DW_OP_plus_uconst operation to the expression if a sub-register is spilled. Later on, PEI will add an offset operation for the stack slot, meaning that we will get expressions of the forms: * {DW_OP_constu #fp-offset, DW_OP_minus, DW_OP_plus_uconst #subreg-offset} * {DW_OP_plus_const #fp-offset, DW_OP_minus, DW_OP_plus_uconst #subreg-offset} The two offset operations should ideally be merged. Reviewers: rnk, aprantl, stoklund Reviewed By: aprantl Subscribers: dblaikie, bjope, nemanjai, JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D51612 llvm-svn: 341659
* Add support for getRegisterByName.Sid Manning2018-09-072-0/+16
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341658
* [DAGCombiner] foldBitcastedFPLogic - Add basic vector supportSimon Pilgrim2018-09-071-8/+8
| | | | | | | | Add support for bitcasts from float type to an integer type of the same element bitwidth. There maybe cases where we need to support different widths (e.g. as SSE __m128i is treated as v2i64) - but I haven't seen cases of this in the wild yet. llvm-svn: 341652
* [NewGVN] Mark function as changed if we erase instructions.Florian Hahn2018-09-071-2/+4
| | | | | | | | | | | | | | | | | | | | | | Currently eliminateInstructions only returns true if any instruction got replaced. In the test case for this patch, we eliminate the trivially dead calls, for which eliminateInstructions not do a replacement and the function is not marked as changed, which is why the inliner crashes while traversing the call graph. Alternatively we could also change eliminateInstructions to return true in case we mark instructions for deletion, but that's slightly more code and doing it at the place where the replacement happens seems safer. Fixes PR37517. Reviewers: davide, mcrosier, efriedma, bjope Reviewed By: bjope Differential Revision: https://reviews.llvm.org/D51169 llvm-svn: 341651
* [MSan] don't access MsanCtorFunction when using KMSANAlexander Potapenko2018-09-071-1/+1
| | | | | | MSan has found a use of uninitialized memory in MSan, fix it. llvm-svn: 341646
* ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.Tim Northover2018-09-075-3/+12
| | | | | | | | | | | Because t2LDREX (& t2STREX) were marked as AddrModeNone, but did allow a FrameIndex operand, rewriteT2FrameIndex asserted. This gives them a proper addressing-mode and tells the rewriter about it so that encodable offsets are exploited and others are rejected. Should fix PR38828. llvm-svn: 341642
* [MSan] Add KMSAN instrumentation to MSan passAlexander Potapenko2018-09-071-72/+310
| | | | | | | | | | | | | | | | | | | | | | | | Introduce the -msan-kernel flag, which enables the kernel instrumentation. The main differences between KMSAN and MSan instrumentations are: - KMSAN implies msan-track-origins=2, msan-keep-going=true; - there're no explicit accesses to shadow and origin memory. Shadow and origin values for a particular X-byte memory location are read and written via pointers returned by __msan_metadata_ptr_for_load_X(u8 *addr) and __msan_store_shadow_origin_X(u8 *addr, uptr shadow, uptr origin); - TLS variables are stored in a single struct in per-task storage. A call to a function returning that struct is inserted into every instrumented function before the entry block; - __msan_warning() takes a 32-bit origin parameter; - local variables are poisoned with __msan_poison_alloca() upon function entry and unpoisoned with __msan_unpoison_alloca() before leaving the function; - the pass doesn't declare any global variables or add global constructors to the translation unit. llvm-svn: 341637
* [AMDGPU] Preliminary patch for divergence driven instruction selection. Fold ↵Alexander Timofeev2018-09-071-3/+11
| | | | | | | | | immediate SMRD offset. Differential revision: https://reviews.llvm.org/D51610 Reviewer: rampitec llvm-svn: 341636
* [PowerPC] Combine ADD to ADDZEQingShan Zhang2018-09-072-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | On the ppc64le platform, if ir has the following form, define i64 @addze1(i64 %x, i64 %z) local_unnamed_addr #0 { entry: %cmp = icmp ne i64 %z, CONSTANT (-32767 <= CONSTANT <= 32768) %conv1 = zext i1 %cmp to i64 %add = add nsw i64 %conv1, %x ret i64 %add } we can optimize it to the form below. when C == 0 --> addze X, (addic Z, -1)) / add X, (zext(setne Z, C))-- \ when -32768 <= -C <= 32767 && C != 0 --> addze X, (addic (addi Z, -C), -1) Patch By: HLJ2009 (Li Jia He) Differential Revision: https://reviews.llvm.org/D51403 Reviewed By: Nemanjai llvm-svn: 341634
* [IndVars] Set Changed when we delete dead instructions. PR38855Max Kazantsev2018-09-071-1/+1
| | | | | | | | | | | IndVars does not set `Changed` flag when it eliminates dead instructions. As result, it may make IR modifications and report that it has done nothing. It leads to inconsistent preserved analyzes results. Differential Revision: https://reviews.llvm.org/D51770 Reviewed By: skatkov llvm-svn: 341633
* Revert "[XRay] Add a BlockVerifier visitor for FDR Records"Dean Michael Berris2018-09-072-183/+0
| | | | | | This reverts commit r341628. llvm-svn: 341631
* [XRay] Add a BlockVerifier visitor for FDR RecordsDean Michael Berris2018-09-072-0/+183
| | | | | | | | | | | | | | | | | | | Summary: This patch implements a `BlockVerifier` type which enforces the invariants of the log structure of FDR mode logs on a per-block basis. This ensures that the data we encounter from an FDR mode log semantically correct (i.e. that records follow the documented "grammar" for FDR mode log records). This is another part of the refactoring of D50441. Reviewers: mboerger, eizan Subscribers: mgorny, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51723 llvm-svn: 341628
* [X86] Fix some incorrect comments. NFCCraig Topper2018-09-071-3/+3
| | | | llvm-svn: 341624
* [PDB] Rename some files in the native reader.Zachary Turner2018-09-077-81/+80
| | | | | | | By calling these NativeType<foo>.cpp, they will all be sorted together, and it also distinguishes the types from the symbols. llvm-svn: 341609
* [PDB] Create a SymbolCache class.Zachary Turner2018-09-077-140/+194
| | | | | | | | | | | | | Part of the responsibility of the native PDB reader is to cache symbols the first time they are accessed, so they can then be looked up by an ID. Furthermore, we need to resolve type indices to records that we vend to the user, and other things. Previously this code was all thrown together a bit haphazardly in the native session class, but it makes sense to collect all of this into a single class whose sole responsibility is to manage the collection of known symbols. llvm-svn: 341608
* [X86] Add RMW ADC patterns with load in operand 1.Craig Topper2018-09-061-8/+22
| | | | | | | | ADC is commutable and the load could be in either operand, but we were only checking operand 0. Ideally we'd mark X86adc_flag as commutable and tablegen would automatically do this, but the EFLAGS register mention is preventing it. llvm-svn: 341606
* Fix error with SmallString implicit conversion.Zachary Turner2018-09-061-3/+1
| | | | llvm-svn: 341597
* [X86] Add isel patterns for commuting X86adc_flag with a load in the LHS.Craig Topper2018-09-062-0/+12
| | | | | | | | The peephole pass likely gets this normally, but we should be doing it during isel. Ideally we'd just make the X86adc_flag pattern SDNPCommutable, but the tablegen doesn't handle that when one of the operands is a register reference. llvm-svn: 341596
* The initial .text section generated in object files was missing theEric Christopher2018-09-066-2/+45
| | | | | | | | | | | | | | | | | | | | SHF_ARM_PURECODE flag when being built with the -mexecute-only flag. All code sections of an ELF must have the flag set for the final .text section to be execute-only, otherwise the flag gets removed. A HasData flag is added to MCSection to aid in the determination that the section is empty. A virtual setTargetSectionFlags is added to MCELFObjectTargetWriter to allow subclasses to set target specific section flags to be added to sections which we then use in the ARM backend to set SHF_ARM_PURECODE. Patch by Ivan Lozano! Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D48792 llvm-svn: 341593
* [SampleFDO] Make sample profile loader unaware of compact format change.Wei Mi2018-09-063-13/+19
| | | | | | | | | | | | | | | | The patch tries to make sample profile loader independent of profile format change. It moves compact format related code into FunctionSamples and SampleProfileReader classes, and sample profile loader only has to interact with those two classes and will be unaware of profile format changes. The cleanup also contain some fixes to further remove the difference between compactbinary format and binary format. After the cleanup using different formats originated from the same profile will generate the same binaries, which we verified by compiling two large server benchmarks w/wo thinlto. Differential Revision: https://reviews.llvm.org/D51643 llvm-svn: 341591
* Fix a configure issue with Visual Studio generators.Zachary Turner2018-09-061-11/+32
| | | | | | | | | | | | | We can't put the unittest source dir map in the configuration specific directory because VS doesn't have a configure-specific directory, instead it only knows this at runtime. So we have to remove this from the path. This in turn means that the path will be slightly different in VS configurations vs non vs configurations. In the former, the source map will be in the parent directory of the executable, and in the latter it will be in the same directory as the executable. So check both. llvm-svn: 341590
* Revert r341413Scott Linder2018-09-063-232/+67
| | | | | | Causes a regression in expensive checks. llvm-svn: 341589
* Output per-function size-info remarksJessica Paquette2018-09-063-16/+119
| | | | | | | | | | | This patch adds per-function size information remarks. Previously, passing -Rpass-analysis=size-info would only give you per-module changes. By adding the ability to do this per-function, it's easier to see which functions contributed the most to size changes. https://reviews.llvm.org/D51467 llvm-svn: 341588
* [LoopPassManager] MemorySSA should be preserved when enabled.Alina Sbirlea2018-09-061-2/+2
| | | | llvm-svn: 341587
* [ARC] Prevent InstPrinter from crashing on unknown condition codes.Tatyana Krasnukha2018-09-061-3/+8
| | | | | | | | | | | | | Summary: Instruction printer shouldn't crash with assertions due to incorrect input data. llvm_unreachable is not intended for runtime error handling. Reviewers: petecoup Reviewed By: petecoup Differential Revision: https://reviews.llvm.org/D51728 llvm-svn: 341581
* Quick fix for -DBUILD_SHARED_LIBS=on build after rL341502Fangrui Song2018-09-061-4/+2
| | | | | | | | libLLVMTestingSupport.so references a symbol in utils/unittest/UnitTestMain/TestMain.cpp (a layering issue) and will cause a link error because of -Wl,-z,defs (cmake/modules/HandleLLVMOptions.cmake) Waiting zturner for a better fix. llvm-svn: 341580
* [ORC] Make RuntimeDyldObjectLinkingLayer2 take memory managers by unique_ptr.Lang Hames2018-09-061-1/+1
| | | | | | | | | | | | The existing memory manager API can not be shared between objects when linking concurrently (since there is no way to know which concurrent allocations were performed on behalf of which object, and hence which allocations would be safe to finalize when finalizeMemory is called). For now, we can work around this by requiring a new memory manager for each object. This change only affects the concurrent version of the ORC APIs. llvm-svn: 341579
* [ORC] Remove the mapSectionAddress method from RuntimeDyldObjectLinkingLayer2.Lang Hames2018-09-061-19/+0
| | | | | | | | Section address mappings can be applied using the RuntimeDyld instance passed to the RuntimeDyld::MemoryManager::notifyObjectLoaded method. Proving an alternate route via RuntimeDyldObjectLinkingLayer2 is redundant. llvm-svn: 341578
* AMDGPU: Remove old hack for function addressesMatt Arsenault2018-09-061-13/+0
| | | | llvm-svn: 341567
* [InstCombine] add xor+not foldsSanjay Patel2018-09-061-0/+16
| | | | | | | | | | This fold is needed to avoid a regression when we try to recommit rL300977. We can't see the most basic win currently because demanded bits changes the patterns: https://rise4fun.com/Alive/plpp llvm-svn: 341559
* ARM64: improve non-zero memset isel by ~2xJF Bastien2018-09-061-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: I added a few ARM64 memset codegen tests in r341406 and r341493, and annotated where the generated code was bad. This patch fixes the majority of the issues by requesting that a 2xi64 vector be used for memset of 32 bytes and above. The patch leaves the former request for f128 unchanged, despite f128 materialization being suboptimal: doing otherwise runs into other asserts in isel and makes this patch too broad. This patch hides the issue that was present in bzero_40_stack and bzero_72_stack because the code now generates in a better order which doesn't have the store offset issue. I'm not aware of that issue appearing elsewhere at the moment. <rdar://problem/44157755> Reviewers: t.p.northover, MatzeB, javed.absar Subscribers: eraman, kristof.beyls, chrib, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51706 llvm-svn: 341558
* Remove unnecessary semicolon to silence -Wpedantic warning. NFCI.Simon Pilgrim2018-09-061-1/+1
| | | | llvm-svn: 341555
* [MSan] store origins for variadic function parameters in ↵Alexander Potapenko2018-09-061-4/+61
| | | | | | | | | | | | | | | | | __msan_va_arg_origin_tls Add the __msan_va_arg_origin_tls TLS array to keep the origins for variadic function parameters. Change the instrumentation pass to store parameter origins in this array. This is a reland of r341528. test/msan/vararg.cc doesn't work on Mips, PPC and AArch64 (because this patch doesn't touch them), XFAIL these arches. Also turned out Clang crashed on i80 vararg arguments because of incorrect origin type returned by getOriginPtrForVAArgument() - fixed it and added a test. llvm-svn: 341554
* [InstCombine] fix formatting in SimplifyDemandedVectorElts->Select; NFCISanjay Patel2018-09-061-12/+16
| | | | | | | | I'm preparing to add the same functionality both here and to the DAG version of this code in D51696 / D51433, so try to make those cases as similar as possible to avoid bugs. llvm-svn: 341545
* [MSan] revert r341528 to unbreak the botsAlexander Potapenko2018-09-061-61/+4
| | | | llvm-svn: 341541
* [LoopInterchange] Cleanup unused variables.Florian Hahn2018-09-061-8/+2
| | | | llvm-svn: 341537
* Fix argument type in MachineInstr::hasPropertyInBundleSven van Haastregt2018-09-061-1/+1
| | | | | | | | | | | | | The MCID::Flag enumeration now has more than 32 items, this means that the hasPropertyBundle argument 'Mask' can overflow. This patch changes the argument to be 64 bits instead. Patch by Mikael Nilsson. Differential Revision: https://reviews.llvm.org/D51596 llvm-svn: 341536
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