summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [MIPS GlobalISel] Select icmpPetar Jovanovic2018-09-103-0/+89
| | | | | | | | | | Select 32bit integer compare instructions for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51489 llvm-svn: 341840
* HotColdSplitting: check that target supports cold calling conventionSebastian Pop2018-09-101-4/+13
| | | | | | | | | Before tagging a function with coldcc make sure the target supports cold calling convention. Without this patch HotColdSplitting pass fails on aarch64 with: fatal error: error in backend: Unsupported calling convention. llvm-svn: 341838
* add flag instead of using a constant [NFC]Sebastian Pop2018-09-101-1/+5
| | | | llvm-svn: 341837
* make flag name more specific to gvn [NFC]Sebastian Pop2018-09-101-2/+2
| | | | llvm-svn: 341836
* InstCombine: move hasOneUse check to the top of foldICmpAddConstantTim Northover2018-09-101-3/+3
| | | | | | | | | | | | There were two combines not covered by the check before now, neither of which actually differed from normal in the benefit analysis. The most recent seems to be because it was just added at the top of the function (naturally). The older is from way back in 2008 (r46687) when we just didn't put those checks in so routinely, and has been diligently maintained since. llvm-svn: 341831
* [Sparc] Move SparcTargetStreamer.h to the MC Desc, where the implementation ↵Benjamin Kramer2018-09-102-4/+3
| | | | | | is already llvm-svn: 341826
* [LLD][COFF] Cleanup error messages / add more coverage testsAlexandre Ganea2018-09-101-1/+1
| | | | | | | | | | | | - Log the reason for a PDB or precompiled-OBJ load failure - Properly handle out-of-date PDB or precompiled-OBJ signature by displaying a corresponding error - Slightly change behavior on PDB failure: any subsequent load attempt from another OBJ would result in the same error message being logged - Slightly change behavior on PDB failure: retry with filename only if previous error was ENOENT ("no such file or directory") - Tests: a. for native PDB errors; b. cover all the cases above Differential Revision: https://reviews.llvm.org/D51559 llvm-svn: 341825
* [Target] Untangle disassemblersBenjamin Kramer2018-09-1015-43/+37
| | | | | | | Disassemblers cannot depend on main target headers. The same is true for MCTargetDesc, but there's a lot more cleanup needed for that. llvm-svn: 341822
* Don't create a temporary vector of loop blocks just to iterate over them.Benjamin Kramer2018-09-103-14/+9
| | | | | | Loop's getBlocks returns an ArrayRef. llvm-svn: 341821
* [GVN] Invalidate cached info for values replaced by equality propagationJohn Brawn2018-09-101-0/+6
| | | | | | | | | When GVN propagates an equality by replacing one value with another it also needs to invalidate the cached information for the value being replaced. Differential Revision: https://reviews.llvm.org/D51218 llvm-svn: 341820
* AMDGPU: Remove function pointer type hackMatt Arsenault2018-09-101-7/+4
| | | | | | | Now the pointer size should always be correct and we don't need to improperly inspect the pointee type. llvm-svn: 341806
* AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bitMatt Arsenault2018-09-101-2/+1
| | | | | | | This will require something to cast. Before this would eliminate the cast, which would result in copies of $noreg. llvm-svn: 341803
* DAG: Handle odd vector sizes in calling conv splittingMatt Arsenault2018-09-102-20/+22
| | | | | | | | | | | | | | This already worked if only one register piece was used, but didn't if a type was split into multiple, unequal sized pieces. Fixes not splitting 3i16/v3f16 into two registers for AMDGPU. This will also allow fixing the ABI for 16-bit vectors in a future commit so that it's the same for all subtargets. llvm-svn: 341801
* [AMDGPU] Prevent sequences of non-instructions disrupting ↵Carl Ritson2018-09-101-2/+9
| | | | | | | | | | | | | | | | | | GCNHazardRecognizer wait state counting Summary: This fixes a bug where a large number of implicit def instructions can fill the GCNHazardRecognizer lookahead buffer causing required NOPs to not be inserted. Reviewers: nhaehnle, arsenm Reviewed By: arsenm Subscribers: sheredom, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D51726 Change-Id: Ie75338f94de704ee5816b05afd0c922c6748a95b llvm-svn: 341798
* [IndVars] Set Changed if rewriteFirstIterationLoopExitValues changes IR. PR38863Max Kazantsev2018-09-101-3/+6
| | | | | | | | | | | Currently, `rewriteFirstIterationLoopExitValues` does not set Changed flag even if it makes changes in the IR. There is no clear evidence that it can cause a crash, but it looks highly suspicious and likely invalid. Differential Revision: https://reviews.llvm.org/D51779 Reviewed By: skatkov llvm-svn: 341779
* [IndVars] Set Changed if sinkUnusedInvariants changes IR. PR38863Max Kazantsev2018-09-101-5/+9
| | | | | | | | | | | Currently, `sinkUnusedInvariants` does not set Changed flag even if it makes changes in the IR. There is no clear evidence that it can cause a crash, but it looks highly suspicious and likely invalid. Differential Revision: https://reviews.llvm.org/D51777 Reviewed By: skatkov llvm-svn: 341777
* Move a transformation routine from LoopUtils to LoopVectorize.Vikram TV2018-09-102-72/+84
| | | | | | | | | | | | | | | | Summary: Move InductionDescriptor::transform() routine from LoopUtils to its only uses in LoopVectorize.cpp. Specifically, the function is renamed as InnerLoopVectorizer::emitTransformedIndex(). This is a child to D51153. Reviewers: dmgreen, llvm-commits Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D51837 llvm-svn: 341776
* Move createMinMaxOp() out of RecurrenceDescriptor.Vikram TV2018-09-102-50/+49
| | | | | | | | | | Reviewers: dmgreen, llvm-commits Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D51838 llvm-svn: 341773
* [Xray] tooling allow MachO format supportDavid Carlier2018-09-101-4/+4
| | | | | | | | | | | | Getting writable xray __DATA sections from MachO as well. Reviewers: dberris Reviewed By: dberris Differential Revision: https://reviews.llvm.org/D51758 llvm-svn: 341772
* [XRay] Remove unused referenceDean Michael Berris2018-09-101-2/+2
| | | | | | | | The reference was only used in the assertion. Follow-up on D51723. llvm-svn: 341771
* [XRay] Add a BlockVerifier visitor for FDR RecordsDean Michael Berris2018-09-102-0/+188
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch implements a `BlockVerifier` type which enforces the invariants of the log structure of FDR mode logs on a per-block basis. This ensures that the data we encounter from an FDR mode log semantically correct (i.e. that records follow the documented "grammar" for FDR mode log records). This is another part of the refactoring of D50441. This is a slightly modified version of rL341628, avoiding the `std::tuple<...>` constructor that is not constexpr in C++11. Reviewers: mboerger, eizan Subscribers: mgorny, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51723 llvm-svn: 341769
* AMDGPU: Use GOT PSV since it has an address space nowMatt Arsenault2018-09-101-2/+2
| | | | llvm-svn: 341768
* AMDGPU: Don't abort on unknown addrspace argumentMatt Arsenault2018-09-101-8/+10
| | | | llvm-svn: 341767
* [X86] Custom type legalize (v2i32 (fp_to_uint v2f64))) without avx512vl by ↵Craig Topper2018-09-091-12/+13
| | | | | | | | | | widening to v4i32 and v4f64 instead of v8i32 and v8f64. Make it aware of x86-experimental-vector-widening-legalization We have isel patterns for v4i32/v4f64 that artificially widen to v8i32/v8f64 so just use that. If x86-experimental-vector-widening-legalization is enabled, we don't need any custom legalization and can just return. I've modified the test RUN lines to cover this case. llvm-svn: 341765
* [SelectionDAG] enhance vector demanded elements to look at a vector select ↵Sanjay Patel2018-09-091-4/+12
| | | | | | | | | | | | | | | | condition operand This is the DAG equivalent of D51433. If we know we're not using all vector lanes, use that knowledge to potentially simplify a vselect condition. The reduction/horizontal tests show that we are eliminating AVX1 operations on the upper half of 256-bit vectors because we don't need those anyway. I'm not sure what the pr34592 test is showing. That's run with -O0; is SimplifyDemandedVectorElts supposed to be running there? Differential Revision: https://reviews.llvm.org/D51696 llvm-svn: 341762
* [X86] Create paddus/psubus from narrower vectors with i8/i16 element types.Craig Topper2018-09-081-8/+12
| | | | | | | | | | | | | | | | | Summary: This patch allows vectors with a power of 2 number of elements and i8/i16 element type to select paddus/psubus instructions. ReplaceNodeResults has been updated to custom widen these operations up to 128 bits like we already do for PAVG. Another step towards fixing PR38691 Reviewers: RKSimon, spatel Reviewed By: RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51818 llvm-svn: 341753
* [X86] Mark the ADCX and ADOX instruction as commutable.Craig Topper2018-09-081-1/+1
| | | | llvm-svn: 341752
* Revert "NFC: use bit_cast more in AArch64AddressingModes"JF Bastien2018-09-081-11/+24
| | | | | | | It seems some bots think std::array is either not trivially-copyable, or isn't the right size. llvm-svn: 341750
* NFC: use bit_cast more in AArch64AddressingModesJF Bastien2018-09-081-24/+11
| | | | llvm-svn: 341749
* [X86] Add commuted isel pattern for the load form of ADCX instructions.Craig Topper2018-09-081-0/+9
| | | | | | This prevents the legacy ADC instruction from being favored over ADCX when the load is in the operand 0. llvm-svn: 341745
* Fix typo in previous commitJF Bastien2018-09-081-1/+1
| | | | llvm-svn: 341742
* ADT: add <bit> header, implement C++20 bit_cast, useJF Bastien2018-09-083-39/+25
| | | | | | | | | | | | | | Summary: I saw a few places that were punning through a union of FP and integer, and that made me sad. Luckily, C++20 adds bit_cast for exactly that purpose. Implement our own version in ADT (without constexpr, leaving us a bit sad), and use it in the few places my grep-fu found silly union punning. This was originally committed as r341728 and reverted in r341730. Reviewers: javed.absar, steven_wu, srhines Subscribers: dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51693 llvm-svn: 341741
* Fix typos. NFCFangrui Song2018-09-082-2/+2
| | | | llvm-svn: 341740
* Remove addBlockByrefAddress(), it is dead code as far as clang is concerned.Adrian Prantl2018-09-083-134/+8
| | | | | | | | | | | | This patch removes addBlockByrefAddress(), it is dead code as far as clang is concerned: Every byref block capture is emitted with a complex expression that is equivalent to what this function does. rdar://problem/31629055 Differential Revision: https://reviews.llvm.org/D51763 llvm-svn: 341737
* [MemorySSA] Relax verification of clobbering accesses.Alina Sbirlea2018-09-071-2/+12
| | | | llvm-svn: 341733
* Fix some of the PDB tests.Zachary Turner2018-09-071-2/+0
| | | | | | | | They were unintentionally calling DIA directly, which requires Windows. We need to pass the -native flag, and this then required fixing up one or two tests. llvm-svn: 341731
* Revert "ADT: add <bit> header, implement C++20 bit_cast, use"JF Bastien2018-09-073-24/+39
| | | | | | Bots sad. Looks like missing std::is_trivially_copyable. llvm-svn: 341730
* [PDB] Support pointer types in the native reader.Zachary Turner2018-09-0710-195/+364
| | | | | | | | | | In order to start testing this, I've added a new mode to llvm-pdbutil which is only really useful for writing tests. It just dumps the value of raw fields in record format. This isn't really ideal and it won't allow us to test some important cases, but it's better than nothing for now. llvm-svn: 341729
* ADT: add <bit> header, implement C++20 bit_cast, useJF Bastien2018-09-073-39/+24
| | | | | | | | | | | | Summary: I saw a few places that were punning through a union of FP and integer, and that made me sad. Luckily, C++20 adds bit_cast for exactly that purpose. Implement our own version in ADT (without constexpr, leaving us a bit sad), and use it in the few places my grep-fu found silly union punning. Reviewers: javed.absar Subscribers: dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51693 llvm-svn: 341728
* [COFF] Implement llvm.global_ctors priorities for MSVC COFF targetsReid Kleckner2018-09-071-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | Summary: MSVC and LLD sort sections ASCII-betically, so we need to use section names that sort between .CRT$XCA (the start) and .CRT$XCU (the default priority). In the general case, use .CRT$XCT12345 as the section name, and let the linker sort the zero-padded digits. Users with low priorities typically want to initialize as early as possible, so use .CRT$XCA00199 for prioties less than 200. This number is arbitrary. Implements PR38552. Reviewers: majnemer, mstorsjo Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51820 llvm-svn: 341727
* [SimplifyIndVar] Avoid generating truncate instructions with non-hoisted ↵Abderrazek Zaafrani2018-09-071-0/+152
| | | | | | | | Laod operand. Differential Revision: https://reviews.llvm.org/D49151 llvm-svn: 341726
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-074-0/+95
| | | | | | | | | | | | | | | | | | Summary: Since the shuffle mask is not exposed as an operand in the native ISel DAG, create a new WebAssembly ISD node exposing the mask. The mask is lowered as sixteen immediate byte indices no matter what type the original vector shuffle was operating on. This CL depends on D51656 Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51659 llvm-svn: 341718
* [AST] Generalize argument specific aliasingPhilip Reames2018-09-072-3/+44
| | | | | | | | | | | | | | AliasSetTracker has special case handling for memset, memcpy and memmove which pre-existed argmemonly on functions and readonly and writeonly on arguments. This patch generalizes it using the AA infrastructure to any call correctly annotated. The motivation here is to cut down on confusion, not performance per se. For most instructions, there is a direct mapping to alias set. However, this is not guaranteed by the interface and was not in fact true for these three intrinsics *and only these three intrinsics*. I kept getting myself confused about this invariant, so I figured it would be good to clearly distinguish between a instructions and alias sets. Calls happened to be an easy target. The nice side effect is that custom implementations of memset/memcpy/memmove - including wrappers discovered by IPO - can now be optimized the same as builts by LICM. Note: The actual removal of the memset/memtransfer specific handling will happen in a follow on NFC patch. It was originally part of this one, but separate for ease of review and rebase. Differential Revision: https://reviews.llvm.org/D50730 llvm-svn: 341713
* [codeview] Add .cv_string directive for testing purposesReid Kleckner2018-09-071-1/+20
| | | | | | | | | | | The main use case for this directive is to allow assembly writers to write their own FPO data strings without going through the .cv_fpo* directive family. I'm experimenting with different RPN programs to fix PR38857, and I figured I should go ahead and make this directive permanent. llvm-svn: 341712
* [MemorySSA] Update MemoryPhi wiring for block splitting to consider if ↵Alina Sbirlea2018-09-072-2/+12
| | | | | | | | | | | | | | | | | identical edges were merged. Summary: Block splitting is done with either identical edges being merged, or not. Only critical edges can be split without merging identical edges based on an option. Teach the memoryssa updater to take this into account: for the same edge between two blocks only move one entry from the Phi in Old to the new Phi in New. Reviewers: george.burgess.iv Subscribers: sanjoy, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D51563 llvm-svn: 341709
* [InstCombine] narrow vector select with padded condition and extracted ↵Sanjay Patel2018-09-071-0/+38
| | | | | | | | | | | | | | | | | | result (PR38691) shuf (sel (shuf NarrowCond, undef, WideMask), X, Y), undef, NarrowMask) --> sel NarrowCond, (shuf X, undef, NarrowMask), (shuf Y, undef, NarrowMask) The motivating case from: https://bugs.llvm.org/show_bug.cgi?id=38691 ...is the last regression test. In that case, we're just left with the narrow select. Note that if we do create new shuffles, they use the existing extraction identity mask, so there's no danger that this transform creates arbitrary shuffles. Differential Revision: https://reviews.llvm.org/D51496 llvm-svn: 341708
* [WebAssembly] Change SIMD lane indices to vec_i8imm_opThomas Lively2018-09-071-4/+4
| | | | | | | | | | | | Summary: To explicitly opt out of LEB encoding for these immediates. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51766 llvm-svn: 341707
* [AArch64] Support reserving x1-7 registers.Nick Desaulniers2018-09-079-52/+79
| | | | | | | | | | | | | | | Summary: Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7. Reviewers: javed.absar, phosek, srhines, nickdesaulniers, efriedma Reviewed By: nickdesaulniers, efriedma Subscribers: niravd, jfb, manojgupta, nickdesaulniers, jyknight, efriedma, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D48580 llvm-svn: 341706
* [X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.Craig Topper2018-09-071-1/+1
| | | | | | The generic type legalizer will scalarize vXi1 instructions getting rid of the vector entirely. Creating wider vector instructions is just going to prevent that. llvm-svn: 341705
* [X86] Don't create X86ISD::AVG nodes from v1iX vectors.Craig Topper2018-09-071-1/+1
| | | | | | | | The type legalizer will try to scalarize this and fail. It looks like there's some other v1iX oddities out there too since we still generated some vector instructions. llvm-svn: 341704
OpenPOWER on IntegriCloud