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* Fix comment in InstCombiner::visitAddrSpaceCast.Manuel Jacob2014-07-161-3/+3
| | | | | | | | In the original version of the patch the behaviour was like described in the comment. This behaviour was changed before committing it without updating the comment. llvm-svn: 213117
* Perform wildcard expansion in Process::GetArgumentVector on Windows (PR17098)Hans Wennborg2014-07-161-19/+71
| | | | | | | | | | | | | | On Windows, wildcard expansion isn't performed by the shell, but left to the program itself. The common way to do this is to link with setargv.obj, which performs the expansion on argc/argv before main is entered. However, we don't use argv in Clang on Windows, but instead call GetCommandLineW so we can handle unicode arguments. This means we have to do wildcard expansion ourselves. A test case will be added on the Clang side. Differential Revision: http://reviews.llvm.org/D4529 llvm-svn: 213114
* Emit warnings if vectorization is forced and fails.Tyler Nowicki2014-07-162-10/+42
| | | | | | | | | | | This patch modifies the existing DiagnosticInfo system to create a generic base class that is inherited to produce diagnostic-based warnings. This is used by the loop vectorizer to trigger a warning when vectorization is forced and fails. Several tests have been added to verify this behavior. Reviewed by: Arnold Schwaighofer llvm-svn: 213110
* Remove TLI from isInTailCallPosition's arguments. NFC.Juergen Ributzka2014-07-163-5/+5
| | | | | | | There is no need to pass on TLI separately to the function. As Eric pointed out the Target Machine already provides everything we need. llvm-svn: 213108
* R600/SI: Allow using f32 rcp / rsq when denormals not handled.Matt Arsenault2014-07-153-10/+31
| | | | | | | These are precise enough to use for OpenCL unless denormals are handled. llvm-svn: 213107
* X86: Simplify X86WindowsTargetObjectFile::getSectionForConstantDavid Majnemer2014-07-151-9/+3
| | | | | | | | | There exists a helper function to abstract away the various differences between ConstantVector, ConstantDataVector, ConstantAggregateZero, etc. Use it to simplify X86WindowsTargetObjectFile::getSectionForConstant. llvm-svn: 213104
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-1513-95/+65
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* [dfsan] Introduce further optimization to reduce the number of union queries.Peter Collingbourne2014-07-151-0/+36
| | | | | | | Specifically, do not compute a union if it is statically known that one shadow set subsumes the other. llvm-svn: 213100
* R600/SI: Fix select on i1Matt Arsenault2014-07-151-0/+3
| | | | llvm-svn: 213096
* R600/SI: Implement less wrong f32 fdivMatt Arsenault2014-07-153-7/+83
| | | | | | | Assuming single precision denormals and accurate sqrt/div are not reported, this passes the OpenCL conformance test. llvm-svn: 213089
* R600: Add predicate for UnsafeFPMathMatt Arsenault2014-07-151-0/+1
| | | | llvm-svn: 213088
* R600: Remove intrinsics that appear to be unusedMatt Arsenault2014-07-151-3/+0
| | | | llvm-svn: 213087
* [RuntimeDyld] Revert r211652 - MachO object GDB registration support.Lang Hames2014-07-153-149/+22
| | | | | | | | The registration scheme used in r211652 violated the read-only contract of MemoryBuffer. This caused crashes in llvm-rtdyld where macho objects were backed by read-only mmap'd memory. llvm-svn: 213086
* [RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of ↵Chris Bieneman2014-07-154-0/+90
| | | | | | | | | | coalescing. The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing. This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825. llvm-svn: 213078
* Revert r213070. It's breaking the build in MCELFStreamer::EmitInstToData(...).Cameron McInally2014-07-151-6/+0
| | | | llvm-svn: 213073
* R600: Implement zero undef variants of ctlz/cttzJan Vesely2014-07-153-0/+17
| | | | | | | | | v2: use ffbh/l if available v3: Rebase on top of Matt's SI patches Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 213072
* [mips] Correct .MIPS.abiflags fp_abi field for -mfpxx and without .moduleDaniel Sanders2014-07-151-1/+1
| | | | | | | | Summary: Previously all the test cases set it after initialization with '.module fp=xx'. Differential Revision: http://reviews.llvm.org/D4489 llvm-svn: 213071
* Add x86 patterns to match a specific add-with-carry. Cameron McInally2014-07-151-0/+6
| | | | llvm-svn: 213070
* [DAGCombiner] Add more rules to fold shuffles.Andrea Di Biagio2014-07-151-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds two new rules to the DAGCombiner: 1. shuffle (shuffle A, Undef, M0), B, M1 -> shuffle A, B, M2 2. shuffle (shuffle A, Undef, M0), A, M1 -> shuffle A, Undef, M2 We only do this if the combined shuffle is legal for the target. Example: ;; define <4 x float> @test(<4 x float> %a, <4 x float> %b) { %1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32><i32 6, i32 0, i32 1, i32 7> %2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32><i32 1, i32 2, i32 4, i32 5> ret <4 x i32> %2 } ;; (using llc -mcpu=corei7 -march=x86-64) Before, the x86 backend generated: pshufd $120, %xmm0, %xmm0 shufps $-108, %xmm0, %xmm1 movaps %xmm1, %xmm0 Now the x86 backend generates: movsd %xmm1, %xmm0 llvm-svn: 213069
* Prune Redundant libdeps in CMake's target_link_libraries and LLVMBuild.txt.NAKAMURA Takumi2014-07-154-4/+4
| | | | | | I checked this with Release+Asserts on x86_64-mingw32. Please restore partially if this were overkill. llvm-svn: 213064
* Silence a warning in conditional expression.Andrea Di Biagio2014-07-151-1/+1
| | | | | | | | Fixes a gcc warning caused by a typo. A redundant assignment operation was accidentally used as the third operand of a conditional expression. No functional change intended. llvm-svn: 213061
* MergeFunc patch from Björn Steinbrink.Stepan Dyatkovskiy2014-07-151-2/+12
| | | | | | | Phabricator ticket: D4246, Don't merge functions with different range metadata on call/invoke. Thanks! llvm-svn: 213060
* AArch64: fall back to generic code for out of range extract/insert.Tim Northover2014-07-151-6/+8
| | | | | | rdar://problem/17624784 llvm-svn: 213059
* Fix typo in commentDavid Majnemer2014-07-151-1/+1
| | | | | | No functionality changed. llvm-svn: 213052
* [FastISel][X86] Remove no longer needed functions.Juergen Ributzka2014-07-151-462/+0
| | | | llvm-svn: 213051
* [FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka2014-07-151-41/+41
| | | | | | | Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively implements the target hook. llvm-svn: 213050
* [FastISel][X86] Implement the FastLowerCall hook.Juergen Ributzka2014-07-151-9/+400
| | | | | | | | | | | | This implements the FastLowerCall hook, which is based on the DoSelectCall function. The implementation is very similar, but the target-independent call lowering part has been factored out. This should also enable patchpoint intrinsic lowering for FastISel on X86. Related to <rdar://problem/17427052>. llvm-svn: 213049
* Revert "[FastISel][X86] Remove no longer needed functions."Juergen Ributzka2014-07-151-244/+315
| | | | | | | | | | Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook." Revert "[FastISel][X86] Implement the FastLowerCall hook." This reverts commit r213035, r213036, and r213037 to make the buildbots happy again. llvm-svn: 213048
* [dfsan] Introduce an optimization to reduce the number of union queries.Peter Collingbourne2014-07-151-1/+34
| | | | | | | Specifically, when building a union query, if we are dominated by an identical query then use the result of that query instead. llvm-svn: 213047
* [dfsan] Move combineShadows to DFSanFunction in preparation for it to use a ↵Peter Collingbourne2014-07-151-18/+16
| | | | | | domtree. llvm-svn: 213046
* Give SplitBlockAndInsertIfThen the ability to update a domtree.Peter Collingbourne2014-07-151-1/+16
| | | | llvm-svn: 213045
* CodeGen: Handle ConstantVector and undef in WinCOFF constant poolsDavid Majnemer2014-07-151-13/+21
| | | | | | | | | | | | The constant pool entry code for WinCOFF assumed that vector constants would be formed using ConstantDataVector, it did not expect to see a ConstantVector. Furthermore, it did not expect undef as one of the elements of the vector. ConstantVectors should be handled like ConstantDataVectors, treat Undef as zero. llvm-svn: 213038
* [FastISel][X86] Remove no longer needed functions.Juergen Ributzka2014-07-151-462/+0
| | | | llvm-svn: 213037
* [FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka2014-07-151-41/+41
| | | | | | | Rename X86VisitIntrinsicCall -> FastLowerIntrinsicCall, which effectively implements the target hook. llvm-svn: 213036
* [FastISel][X86] Implement the FastLowerCall hook.Juergen Ributzka2014-07-151-9/+400
| | | | | | | | | | | | This implements the FastLowerCall hook, which is based on the DoSelectCall function. The implementation is very similar, but the target-independent call lowering part has been factored out. This should also enable patchpoint intrinsic lowering for FastISel on X86. Related to <rdar://problem/17427052>. llvm-svn: 213035
* [FastISel] Insert patchpoint instruction before the target generated call ↵Juergen Ributzka2014-07-151-1/+2
| | | | | | | | | | instruction. The patchpoint instruction should have been inserted before the target generated call instruction to be inside the ADJSTACKDOWN/ADJSTACKUP call sequence window. llvm-svn: 213034
* [FastISel] Fix patchpoint lowering to set the result register.Juergen Ributzka2014-07-151-5/+6
| | | | | | | | Always update the value map with the result register (if there is one), for the patchpoint instruction we created to replace the target-specific call instruction. llvm-svn: 213033
* R600: Add dag combine for copy of an illegal type.Matt Arsenault2014-07-152-1/+56
| | | | | | | | | This helps avoid redundant instructions to unpack, and repack the vectors. Ideally we could recognize that pattern and eliminate it. Currently v4i8 and other small element type vectors are scalarized, so this has the added bonus of avoiding that. llvm-svn: 213031
* Teach computeKnownBits to look through addrspacecast.Matt Arsenault2014-07-151-0/+2
| | | | | | This fixes inferring alignment through an addrspacecast. llvm-svn: 213030
* Document the maximum LLVM IR alignment, which is 1 << 29 or 0.5 GiBReid Kleckner2014-07-151-0/+8
| | | | | | | Add verifier checks. We already check these in the assembly parser, but a frontend producing IR in memory wouldn't hit those checks. llvm-svn: 213027
* Teach GetUnderlyingObject / BasicAA about addrspacecastMatt Arsenault2014-07-152-2/+4
| | | | llvm-svn: 213025
* Revert r212572 "improve BasicAA CS-CS queries", it causes PR20303.Nick Lewycky2014-07-153-142/+126
| | | | llvm-svn: 213024
* [DAGCombiner] Avoid calling method 'isShuffleMaskLegal' on illegal vector types.Andrea Di Biagio2014-07-151-0/+2
| | | | | | | | | | | | | | | | | | This patch fixes a crasher in method 'DAGCombiner::visitOR' due to an invalid call to method 'isShuffleMaskLegal'. On x86, method 'isShuffleMaskLegal' always expects a legal vector value type in input. With this patch, we immediately check if the input OR dag node has a legal vector type; we only try to fold a OR dag node into a single shufflevector if we know that the resulting shuffle will have a legal type. This is to avoid calling method 'isShuffleMaskLegal' on a potentially illegal vector value type. Added a new test-case to file 'CodeGen/X86/combine-or.ll' to verify that DAGCombiner doesn't crash in the attempt to check/combine an OR between shuffles with illegal types. llvm-svn: 213020
* R600: Add denormal handling subtarget features.Matt Arsenault2014-07-145-4/+56
| | | | llvm-svn: 213018
* R600/SI: Default to no single precision denormals.Matt Arsenault2014-07-141-1/+9
| | | | llvm-svn: 213017
* [RuntimeDyld] Handle endiannes differences between the host and target whileLang Hames2014-07-141-14/+19
| | | | | | | | | | reading MachO files magic numbers in RuntimeDyld. This is required now that we're testing cross-platform JITing (via RuntimeDyldChecker), and should fix some issues that David Fang has seen on PPC builds. llvm-svn: 213012
* [X86] Specify all TSFlags bit-offsets symbolicallyAdam Nemet2014-07-141-3/+6
| | | | | | | | | | | | | | | No functional change. The offsets for the other bitfields are specified symbolically. I need to increase the size for one of the earlier fields which is easier after this cleanup. Why these bits are relative to VEXShift is a bit strange but that is for another cleanup. I made sure that the values for the enums are unchanged after this change. llvm-svn: 213011
* CodeGen: Stick constant pool entries in COMDAT sections for WinCOFFDavid Majnemer2014-07-1411-16/+127
| | | | | | | | | | | | | | | | COFF lacks a feature that other object file formats support: mergeable sections. To work around this, MSVC sticks constant pool entries in special COMDAT sections so that each constant is in it's own section. This permits unused constants to be dropped and it also allows duplicate constants in different translation units to get merged together. This fixes PR20262. Differential Revision: http://reviews.llvm.org/D4482 llvm-svn: 213006
* Fix a -Wunused-local-typedefs warningAlp Toker2014-07-141-1/+1
| | | | llvm-svn: 213002
* [DAGCombiner] Add more rules to combine shuffle vector dag nodes.Andrea Di Biagio2014-07-141-0/+44
| | | | | | | | | | | | | | | | This patch teaches the DAGCombiner how to fold a pair of shuffles according to rules: 1. shuffle(shuffle A, B, M0), B, M1) -> shuffle(A, B, M2) 2. shuffle(shuffle A, B, M0), A, M1) -> shuffle(A, B, M3) The new rules would only trigger if the resulting shuffle has legal type and legal mask. Added test 'combine-vec-shuffle-3.ll' to verify that DAGCombiner correctly folds shuffles on x86 when the resulting mask is legal. Also added some negative cases to verify that we avoid introducing illegal shuffles. llvm-svn: 213001
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