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* This patch marks the X86 floating point stack registers ST0-ST7 as reservedPreston Gurd2012-05-011-0/+10
| | | | | | | | | in order to avoid assertion failures in the register scavenger. The assertion failures were “Bad machine code: Using an undefined physical register” and “Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor!”. llvm-svn: 155930
* MC: Unknown assembler directives are now hard errors.Jim Grosbach2012-05-011-1/+1
| | | | | | | | | | | | | | | | Previously, an unsupported/unknown assembler directive issued a warning. That's generally unsafe, and inconsistent with the behaviour of pretty much every system assembler. Now that the MC assemblers are mature enough to be the default on multiple targets, it's reasonable to issue errors for these. For target or platform directives that need to stay warnings, we should add explicit handlers for them in, e.g., ELFAsmParser.cpp, DarwinAsmParser.cpp, et. al., and issue the warning there. rdar://9246275 llvm-svn: 155926
* MC: Remove errant EatToEndOfStatement() in asm parser.Jim Grosbach2012-05-011-3/+1
| | | | | | | | | | | | The caller is already responsible for eating any additional input on the line. Putting an additional EatToEndOfStatement() in ParseStatement() causes an entire extra statement to be consumed when treating warnings as errors. For example, test/MC/macros.s will assert() because the .endmacro directive is missed as a result. rdar://11355843 llvm-svn: 155925
* X86: optimization for max-like structManman Ren2012-05-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | This patch will optimize the following cases on X86 (a > b) ? (a-b) : 0 (a >= b) ? (a-b) : 0 (b < a) ? (a-b) : 0 (b <= a) ? (a-b) : 0 FROM movl %edi, %ecx subl %esi, %ecx cmpl %edi, %esi movl $0, %eax cmovll %ecx, %eax TO xorl %eax, %eax subl %esi, %edi cmovll %eax, %edi movl %edi, %eax rdar: 10734411 llvm-svn: 155919
* X86: Use StackRegister instead of FrameRegister in getFrameIndexReference ↵Alexey Samsonov2012-05-012-0/+14
| | | | | | (to generate debug info for local variables) if stack needs realignment llvm-svn: 155917
* Move MipsDisassembler classes into an anonymous namespace.Benjamin Kramer2012-05-011-0/+4
| | | | llvm-svn: 155915
* Value-initialize global to avoid global construction.Benjamin Kramer2012-05-011-2/+2
| | | | llvm-svn: 155909
* RuntimeDyld cleanup:Eli Bendersky2012-05-014-65/+77
| | | | | | | | | | | - Improved parameter names for clarity - Added comments - emitCommonSymbols should return void because its return value is not being used anywhere - Attempt to reduce the usage of the RelocationValueRef type. Restricts it for a single goal and may serve as a step for eventual removal. llvm-svn: 155908
* YAMLParser: get rid of global ctors & dtors.Benjamin Kramer2012-05-011-2/+0
| | | | llvm-svn: 155907
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-0112-70/+68
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors.Craig Topper2012-05-011-9/+9
| | | | llvm-svn: 155899
* RuntimeDyld code cleanup:Eli Bendersky2012-05-016-30/+38
| | | | | | | | | - There's no point having a different type for the local and global symbol tables. - Renamed SymbolTable to GlobalSymbolTable to clarify the intention - Improved const correctness where relevant llvm-svn: 155898
* Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify ↵Craig Topper2012-05-011-9/+8
| | | | | | Bulldozer feature list. llvm-svn: 155897
* Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711.Craig Topper2012-05-011-1/+12
| | | | llvm-svn: 155896
* Make XOP imply AVX as its needed to legalize the registers types.Craig Topper2012-05-011-1/+2
| | | | llvm-svn: 155891
* Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES ↵Craig Topper2012-05-011-3/+3
| | | | | | and HasCLMUL predicates. llvm-svn: 155890
* Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper2012-05-011-2/+4
| | | | llvm-svn: 155888
* Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper2012-05-011-5/+5
| | | | llvm-svn: 155885
* An instruction in a loop is not guaranteed to be executed just because the loopNick Lewycky2012-05-011-0/+5
| | | | | | has no exit blocks. Fixes PR12706! llvm-svn: 155884
* Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. FixesLang Hames2012-05-011-0/+51
| | | | | | | | | <rdar://problem/11291436>. This is a second attempt at a fix for this, the first was r155468. Thanks to Chandler, Bob and others for the feedback that helped me improve this. llvm-svn: 155866
* Add some constantness. No functionality change.Jakub Staszak2012-04-301-9/+9
| | | | llvm-svn: 155859
* X86: optimization for -(x != 0)Manman Ren2012-04-301-0/+16
| | | | | | | | | | | | | This patch will optimize -(x != 0) on X86 FROM cmpl $0x01,%edi sbbl %eax,%eax notl %eax TO negl %edi sbbl %eax %eax llvm-svn: 155853
* ARM: Diagnostics for out of range fixups.Jim Grosbach2012-04-301-34/+52
| | | | | | | | | | | Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 llvm-svn: 155851
* Fix address calculation error from r155744.Jakob Stoklund Olesen2012-04-301-1/+6
| | | | | | | | | | | | This was exposed by SingleSource/UnitTests/Vector/constpool.c. The computed size of a basic block isn't always a multiple of its known alignment, and that can introduce extra alignment padding after the block. <rdar://problem/11347135> llvm-svn: 155845
* Tidy up. No functional change intended.Chad Rosier2012-04-301-8/+7
| | | | llvm-svn: 155832
* Fix fastcc structure return with fast-isel on x86-32Derek Schuff2012-04-301-0/+2
| | | | | | | | | | | | | | On x86-32, structure return via sret lets the callee pop the hidden pointer argument off the stack, which the caller then re-pushes. However if the calling convention is fastcc, then a register is used instead, and the caller should not adjust the stack. This is implemented with a check of IsTailCallConvention X86TargetLowering::LowerCall but is now checked properly in X86FastISel::DoSelectCall. (this time, actually commit what was reviewed!) llvm-svn: 155825
* Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson2012-04-301-1/+3
| | | | | | | | ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. llvm-svn: 155824
* It doesn't make sense to move symbol relocations to section relocations whenEli Bendersky2012-04-302-26/+27
| | | | | | | | | relocations are resolved. It's much more reasonable to do this decision when relocations are just being added - we have all the information at that point. Also a bit of renaming and extra comments to clarify extensions. llvm-svn: 155819
* Just mark the sign bit as known zero, rather than any other irrelevant bitsDuncan Sands2012-04-301-1/+1
| | | | | | known zero in the LHS. Fixes PR12541. llvm-svn: 155818
* Second attempt at PR12573:Bill Wendling2012-04-302-13/+28
| | | | | | | | | | | Allow the "SplitCriticalEdge" function to split the edge to a landing pad. If the pass is *sure* that it thinks it knows what it's doing, then it may go ahead and specify that the landing pad can have its critical edge split. The loop unswitch pass is one of these passes. It will split the critical edges of all edges coming from a loop to a landing pad not within the loop. Doing so will retain important loop analysis information, such as loop simplify. llvm-svn: 155817
* Use an ArrayRef instead of explicit vector type.Bill Wendling2012-04-301-8/+5
| | | | llvm-svn: 155816
* Code cleanup in RuntimeDyld:Eli Bendersky2012-04-304-72/+95
| | | | | | | | | - Add comments - Change field names to be more reasonable - Fix indentation and naming to conform to coding conventions - Remove unnecessary includes / replace them by forward declatations llvm-svn: 155815
* Remove hack from r154987. The problem persists even with it, so it's not ↵Bill Wendling2012-04-301-11/+1
| | | | | | even a good hack. llvm-svn: 155813
* No need to normalize index before calling Extract128BitVectorCraig Topper2012-04-301-12/+11
| | | | llvm-svn: 155811
* Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT ↵Pete Cooper2012-04-302-97/+534
| | | | | | emitter. Needs some major refactoring as these two code emitters are almost identical llvm-svn: 155810
* Make sure HoistInsertPosition finds a position that is dominated by allRafael Espindola2012-04-301-1/+1
| | | | | | inputs. llvm-svn: 155809
* Remove unneeded casts. No functionality change.Jakub Staszak2012-04-291-11/+11
| | | | llvm-svn: 155800
* Simplify code a bit. No functional change intended.Craig Topper2012-04-291-4/+3
| | | | llvm-svn: 155798
* Update the documentation of CellSPU, in case it gets removed in 3.1.Kalle Raiskila2012-04-291-0/+14
| | | | llvm-svn: 155797
* RegisterPressure: ArrayRefize some functions for better readability. No ↵Benjamin Kramer2012-04-292-38/+40
| | | | | | functionality change. llvm-svn: 155795
* Fix some formatting, grammar and style issues and add a couple of missing ↵Eli Bendersky2012-04-295-28/+30
| | | | | | comments. llvm-svn: 155793
* Don't update spill weights when joining intervals.Jakob Stoklund Olesen2012-04-281-25/+0
| | | | | | We don't compute spill weights until after coalescing anyway. llvm-svn: 155766
* Spring cleaning - Delete dead code.Jakob Stoklund Olesen2012-04-281-12/+0
| | | | llvm-svn: 155765
* Fix a problem with blocks that need to be split twice.Jakob Stoklund Olesen2012-04-281-3/+5
| | | | | | | | | The code could search past the end of the basic block when there was already a constant pool entry after the block. Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c llvm-svn: 155753
* Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-281-26/+58
| | | | | | | | | | This time, also fix the caller of AddGlue to properly handle incomplete chains. AddGlue had failure modes, but shamefully hid them from its caller. It's luck ran out. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155749
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-2/+22
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-272-3/+3
| | | | | | Make the operand order of the instruction match that of the asm syntax. llvm-svn: 155747
* Revert r155745Derek Schuff2012-04-271-2/+0
| | | | llvm-svn: 155746
* Fix fastcc structure return with fast-isel on x86-32Derek Schuff2012-04-271-0/+2
| | | | | | | | | | | | On x86-32, structure return via sret lets the callee pop the hidden pointer argument off the stack, which the caller then re-pushes. However if the calling convention is fastcc, then a register is used instead, and the caller should not adjust the stack. This is implemented with a check of IsTailCallConvention X86TargetLowering::LowerCall but is now checked properly in X86FastISel::DoSelectCall. llvm-svn: 155745
* Track worst case alignment padding more accurately.Jakob Stoklund Olesen2012-04-271-42/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, ARMConstantIslandPass would conservatively compute the address of an aligned basic block as: RoundUpToAlignment(Offset + UnknownPadding) This worked fine for the layout algorithm itself, but it could fool the verify() function because it accounts for alignment padding twice: Once when adding the worst case UnknownPadding, and again by rounding up the fictional block offset. This meant that when optimizeThumb2Instructions would shrink an instruction, the conservative distance estimate could grow. That shouldn't be possible since the woorst case alignment padding wss already included. This patch drops the use of RoundUpToAlignment, and depends only on worst case padding to compute conservative block offsets. This has the weird effect that the computed offset for an aligned block may not be aligned. The important difference is that shrinking an instruction can never cause the estimated distance between two instructions to grow. The estimated distance is always larger than the real distance that only the assembler knows. <rdar://problem/11339352> llvm-svn: 155744
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