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* Fix a goof with my previous commit by completely returning when weChandler Carruth2012-05-041-1/+1
| | | | | | detect an in-eligible block rather than just breaking out of the loop. llvm-svn: 156166
* Hoist a safety assert from the extraction method into the constructionChandler Carruth2012-05-041-9/+13
| | | | | | of the extractor itself. llvm-svn: 156164
* Move the CodeExtractor utility to a dedicated header file / source file,Chandler Carruth2012-05-043-166/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | and expose it as a utility class rather than as free function wrappers. The simple free-function interface works well for the bugpoint-specific pass's uses of code extraction, but in an upcoming patch for more advanced code extraction, they simply don't expose a rich enough interface. I need to expose various stages of the process of doing the code extraction and query information to decide whether or not to actually complete the extraction or give up. Rather than build up a new predicate model and pass that into these functions, just take the class that was actually implementing the functions and lift it up into a proper interface that can be used to perform code extraction. The interface is cleaned up and re-documented to work better in a header. It also is now setup to accept the blocks to be extracted in the constructor rather than in a method. In passing this essentially reverts my previous commit here exposing a block-level query for eligibility of extraction. That is no longer necessary with the more rich interface as clients can query the extraction object for eligibility directly. This will reduce the number of walks of the input basic block sequence by quite a bit which is useful if this enters the normal optimization pipeline. llvm-svn: 156163
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-043-12/+23
| | | | | | | | This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
* Fix some loops to match coding standards. No functional change intended.Craig Topper2012-05-041-6/+8
| | | | llvm-svn: 156159
* Fix up some spacing. No functional change.Craig Topper2012-05-041-6/+6
| | | | llvm-svn: 156158
* Simplify broadcast lowering code. No functional change intended.Craig Topper2012-05-041-17/+7
| | | | llvm-svn: 156157
* Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.Craig Topper2012-05-041-5/+8
| | | | llvm-svn: 156156
* Add 'landingpad' instructions to the list of instructions to ignore.Bill Wendling2012-05-041-7/+9
| | | | | | Also combine the code in the 'assert' statement. llvm-svn: 156155
* Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper2012-05-041-22/+16
| | | | llvm-svn: 156154
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-046-121/+30
| | | | | | This information in now computed by TableGen. llvm-svn: 156152
* Use SuperRegClassIterator for findRepresentativeClass().Jakob Stoklund Olesen2012-05-041-26/+15
| | | | | | | | The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
* Initialize SparcInstrInfo before SparcTargetLowering.Jakob Stoklund Olesen2012-05-042-2/+3
| | | | | | | The TargetLowering construction needs to use a valid TargetRegisterInfo instance. llvm-svn: 156146
* Add a SuperRegClassIterator class.Jakob Stoklund Olesen2012-05-041-15/+13
| | | | | | | | This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. llvm-svn: 156144
* A pile of long over-due refactorings here. There are some very, *very*Chandler Carruth2012-05-043-43/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | minor behavior changes with this, but nothing I have seen evidence of in the wild or expect to be meaningful. The real goal is unifying our logic and simplifying the interfaces. A summary of the changes follows: - Make 'callIsSmall' actually accept a callsite so it can handle intrinsics, and simplify callers appropriately. - Nuke a completely bogus declaration of 'callIsSmall' that was still lurking in InlineCost.h... No idea how this got missed. - Teach the 'isInstructionFree' about the various more intelligent 'free' heuristics that got added to the inline cost analysis during review and testing. This mostly surrounds int->ptr and ptr->int casts. - Switch most of the interesting parts of the inline cost analysis that were essentially computing 'is this instruction free?' to use the code metrics routine instead. This way we won't keep duplicating logic. All of this is motivated by the desire to allow other passes to compute a roughly equivalent 'cost' metric for a particular basic block as the inline cost analysis. Sadly, re-using the same analysis for both is really messy because only the actual inline cost analysis is ever going to go to the contortions required for simplification, SROA analysis, etc. llvm-svn: 156140
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-0/+30
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-033-42/+99
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Factor the logic for testing whether a basic block is viable for codeChandler Carruth2012-05-031-14/+21
| | | | | | | | | | | extraction into a public interface. Also clean it up and apply it more consistently such that we check for landing pads *anywhere* in the extracted code, not just in single-block extraction. This will be used to guide decisions in passes that are planning to eventually perform a round of code extraction. llvm-svn: 156114
* remove calls to calloc if the allocated memory is not used (it was already ↵Nuno Lopes2012-05-032-3/+3
| | | | | | | | being done for malloc) fix a few typos found by Chad in my previous commit llvm-svn: 156110
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0314-93/+4967
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
* add support for calloc to objectsize loweringNuno Lopes2012-05-032-5/+57
| | | | llvm-svn: 156102
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | llvm-svn: 156077
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
| | | | | | This adds new instructions for Hexagon V4 architecture. llvm-svn: 156071
* replace 'break's with 'return 0' in visitCallInst code for objectsize, since ↵Nuno Lopes2012-05-031-5/+5
| | | | | | | | there is no need to fallback to visitCallSite. This gives a 0.9% in a test case llvm-svn: 156069
* Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper2012-05-031-3/+3
| | | | | | vector elements. llvm-svn: 156060
* Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ↵Craig Topper2012-05-032-21/+36
| | | | | | lower half correctly. Missed in r155982. llvm-svn: 156059
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-031-15/+16
| | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 llvm-svn: 156048
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-033-8/+40
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
* Whitespace cleanup.Bill Wendling2012-05-021-87/+80
| | | | llvm-svn: 156034
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-021-0/+18
| | | | | | just like it now knows for FMULs. llvm-svn: 156029
* For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd2012-05-021-4/+4
| | | | | | | and Hybrid for 32 bit, since benchmarks show ILP scheduling is better most of the time. llvm-svn: 156028
* Change the Intel Atom detection code to recognizePreston Gurd2012-05-022-3/+5
| | | | | | Lincroft and Medfield. llvm-svn: 156025
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-021-0/+3
| | | | llvm-svn: 156023
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+2
| | | | llvm-svn: 156019
* Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor2012-05-022-0/+150
| | | | | | be used by clang-tblgen. llvm-svn: 156000
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-024-68/+171
| | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. llvm-svn: 155996
* Revert r155853Manman Ren2012-05-021-16/+0
| | | | | | | | The commit is intended to fix rdar://10961709. But it is the root cause of PR12720. Revert it for now. llvm-svn: 155992
* [tsan] typo and style (thanks to Nick Lewycky)Kostya Serebryany2012-05-021-9/+9
| | | | llvm-svn: 155986
* The value held in the vector may be RAUW'ed by some of the canonicalizationBill Wendling2012-05-021-2/+3
| | | | | | | methods. Use a weak value handle to keep up with this. PR12245 llvm-svn: 155984
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-4/+8
| | | | llvm-svn: 155983
* Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support ↵Craig Topper2012-05-024-36/+90
| | | | | | for AsmPrinter. llvm-svn: 155982
* Fix the implementation of MachOObjectFile::isSectionZeroInit so it follows ↵Eli Friedman2012-05-021-4/+6
| | | | | | the MachO spec. llvm-svn: 155976
* Tidy up. Naming conventions.Jim Grosbach2012-05-011-16/+16
| | | | llvm-svn: 155960
* Remove unneeded break.Jakub Staszak2012-05-011-1/+0
| | | | llvm-svn: 155959
* Use dyn_cast instead of checking opcode and cast.Jakub Staszak2012-05-011-2/+1
| | | | llvm-svn: 155957
* Remove trailing spaces.Jakub Staszak2012-05-011-43/+43
| | | | llvm-svn: 155956
* Strip the pointer casts off of allocas so that the selection DAG can find them.Bill Wendling2012-05-011-1/+1
| | | | | | PR10799 llvm-svn: 155954
* Target independent Hexagon Packetizer fix.Sirish Pande2012-05-011-55/+36
| | | | llvm-svn: 155947
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+11
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 llvm-svn: 155946
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
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