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* Don't look for empty live ranges in the unions.Jakob Stoklund Olesen2012-05-121-1/+4
| | | | | | | | | Empty live ranges represent undef and still get allocated, but they won't appear in LiveIntervalUnions. Patch by Patrik Hägglund! llvm-svn: 156685
* Insert instructions to the entry basic block which initializes the globalAkira Hatanaka2012-05-121-35/+52
| | | | | | | | | | | | | | | | | | pointer register. This is the first of the series of patches which clean up the way global pointer register is used. The patches will make the following improvements: - Make $gp an allocatable temporary register rather than reserving it. - Use a virtual register as the global pointer register and let the register allocator decide which register to assign to it or whether spill/reloads are needed. - Make sure $gp is valid at the entry of a called function, which is necessary for functions using lazy binding. - Remove the need for emitting .cprestore and .cpload directives. llvm-svn: 156671
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-111-1/+2
| | | | llvm-svn: 156663
* Revert 156658.Chad Rosier2012-05-111-2/+1
| | | | llvm-svn: 156662
* [fast-isel] Fast-isel doesn't use the expect intrinsic.Chad Rosier2012-05-111-1/+2
| | | | llvm-svn: 156658
* [Support/StringRef] Add find_last_not_of and {r,l,}trim.Michael J. Spencer2012-05-111-0/+26
| | | | llvm-svn: 156652
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+4
| | | | llvm-svn: 156646
* Updated instruction table due to addded intrinsics.Brendon Cahoon2012-05-111-1880/+1943
| | | | llvm-svn: 156644
* Remove warnings from HexagonVLIWPacketizer.Sirish Pande2012-05-111-3/+3
| | | | llvm-svn: 156636
* Hexagon constant extender support.Brendon Cahoon2012-05-1115-339/+3626
| | | | | | Patch by Jyotsna Verma. llvm-svn: 156634
* Typo.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156633
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier2012-05-111-12/+2
| | | | | | Minor cleanup. llvm-svn: 156632
* Hexagon V5 intrinsics support.Sirish Pande2012-05-113-615/+1061
| | | | llvm-svn: 156631
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-4/+21
| | | | | | | | retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
* objectsize: add a few more tests and fix a bugNuno Lopes2012-05-111-1/+1
| | | | llvm-svn: 156625
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
| | | | | | | | to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156621
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-114-130/+350
| | | | llvm-svn: 156615
* Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg2012-05-114-16/+35
| | | | | | | This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-112-0/+5
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-112-3/+9
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Fix a misleading comment.Akira Hatanaka2012-05-111-1/+1
| | | | llvm-svn: 156603
* Tidy up. Trailing whitespace.Jim Grosbach2012-05-1112-35/+35
| | | | llvm-svn: 156602
* Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman2012-05-111-1/+1
| | | | llvm-svn: 156600
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-112-27/+128
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman2012-05-113-0/+8
| | | | | | but it generates int3 on x86 instead of ud2. llvm-svn: 156593
* Allow unique_file to take a mode for file permissions, but defaultEric Christopher2012-05-112-5/+8
| | | | | | | | to user only read/write. Part of rdar://11325849 llvm-svn: 156591
* Fix intendation.Chad Rosier2012-05-101-1/+1
| | | | llvm-svn: 156589
* objectsize: add support for GEPs with non-constant indexesNuno Lopes2012-05-103-34/+34
| | | | | | add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag llvm-svn: 156585
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-103-223/+426
| | | | llvm-svn: 156579
* Add support for the 'X' inline asm operand modifier.Eric Christopher2012-05-101-4/+16
| | | | | | Patch by Jack Carter. llvm-svn: 156577
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-101-0/+2
| | | | llvm-svn: 156576
* misched: tracing register pressure heuristics.Andrew Trick2012-05-101-6/+22
| | | | llvm-svn: 156575
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-101-38/+144
| | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-101-2/+8
| | | | llvm-svn: 156573
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-101-11/+44
| | | | llvm-svn: 156572
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-103-39/+112
| | | | | | scheduling. llvm-svn: 156571
* Hexagon V5 Support - V5 td file.Sirish Pande2012-05-101-0/+626
| | | | llvm-svn: 156569
* Hexagon V5 FP Support.Sirish Pande2012-05-1014-194/+519
| | | | llvm-svn: 156568
* RegPressure: API for speculatively checking instruction pressure.Andrew Trick2012-05-102-1/+229
| | | | | | | | | Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. llvm-svn: 156561
* RegPressure: fix array index iteration style.Andrew Trick2012-05-101-8/+8
| | | | llvm-svn: 156560
* Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.Dan Gohman2012-05-102-3/+50
| | | | llvm-svn: 156558
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-102-127/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* Rewrite ScalarEvolution::hasOperand to use an explicit worklist insteadDan Gohman2012-05-101-35/+50
| | | | | | of recursion, to avoid excessive stack usage on deep expressions. llvm-svn: 156554
* teach DSE and isInstructionTriviallyDead() about callocNuno Lopes2012-05-102-4/+17
| | | | llvm-svn: 156553
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-102-27/+127
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Fix a problem with incomplete equality testing of PHINodes in Joel Jones2012-05-101-1/+8
| | | | | | | | | | | | | | | | | | | | Instruction::IsIdenticalToWhenDefined. This manifested itself when inlining two calls to the same function. The inlined function had a switch statement that returned one of a set of global variables. Without this modification, the two phi instructions that chose values from the branches of the switch instruction inlined from the callee were considered equivalent and jump-threading replaced a load for the first switch value with a phi selecting from the second switch, thereby producing incorrect code. This patch has been tested with "make check-all", "lnt runteste nt", and llvm self-hosted, and on the original program that had this problem, wireshark. <rdar://problem/11025519> llvm-svn: 156548
* Fix merge-typo and cleanupNadav Rotem2012-05-101-5/+3
| | | | llvm-svn: 156541
* AVX2: Add an additional broadcast idiom.Nadav Rotem2012-05-101-2/+5
| | | | llvm-svn: 156540
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