summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix build.Zachary Turner2015-05-011-1/+1
| | | | llvm-svn: 236343
* [llvm-pdbdump] Support dynamic load address and external symbols.Zachary Turner2015-05-011-3/+11
| | | | | | | | | | | This patch adds the --load-address command line option to llvm-pdbdump, which dumps all addresses assuming the module has loaded at the specified address. Additionally, this patch adds an option to llvm-pdbdump to support dumping of public symbols (i.e. symbols with external linkage). llvm-svn: 236342
* Reapply [RuntimeDyldELF] Fold Placeholder into AddendKeno Fischer2015-05-013-192/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reapplies r235060 and 235070, which were reverted because of test failures in LLDB. The failure was caused because at moment RuntimeDyld is processing relocations for all sections, irrespective of whether we actually load them into memory or not, but RuntimeDyld was not actually remembering where in memory the unrelocated section is. This commit includes a fix for that issue by remembering that pointer, though the longer term fix should be to stop processing unneeded sections. Original Summary: This allows us to get rid of the original unrelocated object file after we're done processing relocations (but before applying them). MachO and COFF already do not require this (currently we have temporary hacks to prevent ownership from being released, but those are brittle and should be removed soon). The placeholder mechanism allowed the relocation resolver to look at original object file to obtain more information that are required to apply the relocations. This is usually necessary in two cases: - For relocations targetting sub-word memory locations, there may be pieces of the instruction at the target address which we should not override. - Some relocations on some platforms allow an extra addend to be encoded in their immediate fields. The problem is that in the second case the information cannot be recovered after the relocations have been applied once because they will have been overridden. In the first case we also need to be careful to not use any bits that aren't fixed and may have been overriden by applying a first relocation. In the past both have been fixed by just looking at original object file. This patch attempts to recover the information from the first by looking at the relocated object file, while the extra addend in the second case is read upon relocation processing and addend to the regular addend. I have tested this on X86. Other platforms represent my best understanding of how those relocations should work, but I may have missed something because I do not have access to those platforms. We will keep the ugly workarounds in place for a couple of days, so this commit can be reverted if it breaks the bots. Differential Revision: http://reviews.llvm.org/D9028 llvm-svn: 236341
* Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"Reid Kleckner2015-05-017-343/+6
| | | | | | This reverts commit r236339, it breaks the win32 clang-cl self-host. llvm-svn: 236340
* [WinEH] Add an EH registration and state insertion pass for 32-bit x86Reid Kleckner2015-05-017-6/+343
| | | | | | | | | | | | | | | | | This pass is responsible for constructing the EH registration object that gets linked into fs:00, which is all it does in this change. In the future, it will also insert stores to update the EH state number. I considered keeping this functionality in WinEHPrepare, but it's pretty separable and X86 specific. It has conceptually very little to do with the task of WinEHPrepare, which is currently outlining. WinEHPrepare is also in theory useful on ARM, but this logic is pretty x86 specific. Reviewers: andrew.w.kaylor, majnemer Differential Revision: http://reviews.llvm.org/D9422 llvm-svn: 236339
* [ARM] Transfer the internal flag in thumb2 size reduction.Pete Cooper2015-05-011-1/+4
| | | | | | | | | | Converting from t2LDRs to tLDRr caused the shift argument to drop the internal flag. This would then throw machine verifier errors. Unfortunately i'm having trouble reducing a test case. I'm going to keep trying, but so far its a scary combination of machine sinking, an 'and i1', loads feeding loads, and a bunch of code which shouldn't change IT block formation, but does. Its not useful to commit a test in that state as we have no way of knowing if it even hits this code reliably in future. rdar://problem/20752113 llvm-svn: 236333
* YAML: Fix the output of sequences that contain flow sequences. Alex Lorenz2015-05-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug where the YAML Output class emitted a sequence of flow sequences without the '-' characters. Before: seq: [ a, b ] [ c, d ] After: seq: - [ a, b ] - [ c, d ] Reviewers: Justin Bogner Differential Revision: http://reviews.llvm.org/D9206 llvm-svn: 236329
* ARM: Align functions containing Thumb-2 jump tables to 4 bytes.Peter Collingbourne2015-05-011-0/+4
| | | | | | | | | Functions with jump tables need an alignment of 4 because they use the ADR instruction, which aligns the PC to 4 bytes before adding an offset. Differential Revision: http://reviews.llvm.org/D9424 llvm-svn: 236327
* [Sparc] Repair fixups in little endian mode.James Y Knight2015-05-011-12/+57
| | | | | | Differential Revision: http://reviews.llvm.org/D9434 llvm-svn: 236324
* Fix omission from adding sparcel (original http://reviews.llvm.org/D9263)Douglas Katzman2015-05-011-0/+1
| | | | | | | | "obviously" it needs to go in parseArch *and* getArchTypeForLLVMName. Differential Revision: http://reviews.llvm.org/D9436 llvm-svn: 236322
* [mips] [IAS] Fix error messages for using LI with 64-bit immediates.Toma Tabacu2015-05-011-12/+13
| | | | | | | | | | | | | | | | Summary: LI should never accept immediates larger than 32 bits. The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9289 llvm-svn: 236313
* [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.Toma Tabacu2015-05-011-20/+35
| | | | | | | | | | | | | | | | | | | Summary: Generate one DSLL32 of 0 instead of two consecutive DSLL of 16. In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned. This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases. It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8974 llvm-svn: 236311
* [SelectionDAG] Unary vector constant folding integer legality fixesSimon Pilgrim2015-05-011-5/+25
| | | | | | | | | | | | This patch fixes issues with vector constant folding not correctly handling scalar input operands if they require implicit truncation - this was tested with llvm-stress as recommended by Patrik H Hagglund. The patch ensures that integer input scalars from a build vector are correctly truncated before folding, and that constant integer scalar results are promoted to a legal type before inclusion in the new folded build vector. I have added another crash test case and also a test for UINT_TO_FP / SINT_TO_FP using an non-truncated scalar input, which was failing before this patch. Differential Revision: http://reviews.llvm.org/D9282 llvm-svn: 236308
* R600/SI: Add VCC as an implict def of SI_KILLTom Stellard2015-05-011-3/+6
| | | | | | When SI_KILL has a register operand, its lowered form writes to vcc. llvm-svn: 236307
* R600/SI: Fix verifier errors from the SIAnnotateControlFlow passTom Stellard2015-05-011-1/+9
| | | | | | | | | | | | | This pass was generating 'Instruction does not dominate all uses!' errors for programs which had loops with a condition variable that depended on the result of a phi instruction from outside of the loop. The pass was inserting new phi nodes outside of the loop which used values defined inside the loop. http://bugs.freedesktop.org/show_bug.cgi?id=90056 llvm-svn: 236306
* [ARM] optimizeSelect should clear kill flags.Pete Cooper2015-04-301-0/+7
| | | | | | | | | | | | If we move an instruction from one block down to a MOVC and predicate it, then the original instruction could be moved in to a loop. In this case, its invalid for any kill flags to remain on there. Fails with -verfy-machineinstrs. rdar://problem/20752113 llvm-svn: 236290
* InstrProf: Instrumenter support for setting profile output from command lineJustin Bogner2015-04-301-3/+23
| | | | | | | | | | | | | | | This change is the second of 3 patches to add support for specifying the profile output from the command line via -fprofile-instr-generate=<path>, where the specified output path/file will be overridden by the LLVM_PROFILE_FILE environment variable. This patch adds the necessary support to the llvm instrumenter, specifically a new member of GCOVOptions for clang to save the specified filename, and support for calling the new compiler-rt interface from __llvm_profile_init. Patch by Teresa Johnson. Thanks! llvm-svn: 236288
* Fix typoMatt Arsenault2015-04-301-1/+1
| | | | llvm-svn: 236283
* Commute the internal flag on MachineOperands.Pete Cooper2015-04-301-0/+4
| | | | | | | | | | | | | | When commuting a thumb instruction in the size reduction pass, thumb instructions are represented as a bundle and so some operands may be marked as internal. The internal flag has to move with the operand when commuting. This test is sensitive to register allocation so can't specifically check that this error was happening, but so long as it continues to pass with -verify then hopefully its still ok. rdar://problem/20752113 llvm-svn: 236282
* Fix -Wpessimizing-move warnings by removing std::move calls.Richard Trieu2015-04-302-3/+3
| | | | llvm-svn: 236278
* Remove unnecessary break.Rafael Espindola2015-04-301-1/+0
| | | | llvm-svn: 236275
* [AArch64] Fix bad register class constraint in fast-isel for TST instruction.Quentin Colombet2015-04-301-1/+4
| | | | | | rdar://problem/20748715 llvm-svn: 236273
* Don't always apply kill flag in thumb2 ABS pseudo expansion.Pete Cooper2015-04-301-1/+2
| | | | | | | | | The expansion for t2ABS was always setting the kill flag on the rsb instruction. It should instead only be set on rsb if it was set on the original ABS instruction. rdar://problem/20752113 llvm-svn: 236272
* [X86] Use 4 byte preferred aggregate alignment on Win32Reid Kleckner2015-04-301-1/+1
| | | | | | | | | | | | | This helps reduce the frequency of stack realignment prologues in 32-bit X86 Windows code. Before this change and the corresponding clang change, we would take the max of the type preferred alignment and the explicit alignment on the alloca. If you don't override aggregate alignment in datalayout, you get a default of 8. This dates back to 2007 / r34356, and changing it seems prohibitively difficult at this point. llvm-svn: 236270
* InstCombineSimplifyDemanded: Remove nsw/nuw flags when optimizing demanded bitsMatthias Braun2015-04-301-102/+15
| | | | | | | | | | | | | | | | | | | | | | | | | When optimizing demanded bits of the operands of an Add we have to remove the nsw/nuw flags as we have no guarantee anymore that we don't wrap. This is legal here because the top bit is not demanded. In fact this operaion was already performed but missed in the case of an Add with a constant on the right side. To fix this this patch refactors the code to unify the code paths in SimplifyDemandedUseBits() handling of Add/Sub: - The transformation of Add->Or is removed from the simplify demand code because the equivalent transformation exists in InstCombiner::visitAdd() - KnownOnes/KnownZero are not adjusted for Add x, C anymore as computeKnownBits() already performs these computations. - The simplification of the operands is unified. In this new version constant on the right side of a Sub are shrunk now as I could not find a reason why not to do so. - The special case for clearing nsw/nuw in ShrinkDemandedConstant() is not necessary anymore as the caller does that already. Differential Revision: http://reviews.llvm.org/D9415 llvm-svn: 236269
* InstCombine: Move Sub->Xor rule from SimplifyDemanded to InstCombineMatthias Braun2015-04-302-10/+13
| | | | | | | | | | The rule that turns a sub to xor if the LHS is 2^n-1 and the remaining bits are known zero, does not use the demanded bits at all: Move it to the normal InstCombine code path. Differential Revision: http://reviews.llvm.org/D9417 llvm-svn: 236268
* Simplify the creation of compressed debug sections.Rafael Espindola2015-04-301-106/+33
| | | | | | | | | | This is actually fairly simple in the current code layout: Check if we should compress just before writing out and everything else just works. This removes the last case in which the object writer was creating a fragment. llvm-svn: 236267
* Replace unreachable code with llvm_unreachable.Rafael Espindola2015-04-301-1/+1
| | | | llvm-svn: 236261
* Don't create a MCSectionData when we don't have to.Rafael Espindola2015-04-301-11/+7
| | | | llvm-svn: 236260
* Fix for PR23103. Correctly propagate the 'IsUndef' flag to the register ↵Andrea Di Biagio2015-04-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | operands of a commuted instruction. Revision 220239 exposed a latent bug in method 'TargetInstrInfo::commuteInstruction'. When commuting the operands of a machine instruction, method 'commuteInstruction' didn't correctly propagate the 'IsUndef' flag to the register operands of the new (commuted) instruction. Before this patch, the following instruction: %vreg4<def> = VADDSDrr %vreg14, %vreg5<undef>; FR64:%vreg4,%vreg14,%vreg5 was wrongly converted by method 'commuteInstruction' into: %vreg4<def> = VADDSDrr %vreg5, %vreg14<undef>; FR64:%vreg4,%vreg5,%vreg14 The correct instruction should have been: %vreg4<def> = VADDSDrr %vreg5<undef>, %vreg14; FR64:%vreg4,%vreg5,%vreg14 This patch fixes the problem in method 'TargetInstrInfo::commuteInstruction'. When swapping the operands of a machine instruction, we now make sure that 'IsUndef' flags are correctly set. Added test case 'pr23103.ll'. Differential Revision: http://reviews.llvm.org/D9406 llvm-svn: 236258
* Avoid an extra loop over the sections.Rafael Espindola2015-04-301-7/+1
| | | | | | Add string to the section header string table as we add sections. llvm-svn: 236257
* Make the section table a member of ELFObjectWriter.Rafael Espindola2015-04-301-52/+43
| | | | | | | This avoids passing it around and lets us build a small helper to add a section to the table. llvm-svn: 236255
* Nothing inherits from this, drop the protected:Rafael Espindola2015-04-301-2/+0
| | | | llvm-svn: 236253
* Mips: Remove dead declarationMatt Arsenault2015-04-301-3/+0
| | | | llvm-svn: 236250
* MachineVerifier: Don't crash if MachineOperand has no parentMatt Arsenault2015-04-301-2/+12
| | | | | | | | If you somehow added a MachineOperand to an instruction that did not have the parent set, the verifier would crash since it attempts to use the operand's parent. llvm-svn: 236249
* Don't rewrite jumps to empty BBs to landing pads.Pete Cooper2015-04-301-0/+5
| | | | | | | | | | | | In the test case here, the 'unreachable' BB was removed by BranchFolding because its empty. It then rewrote the jump from 'entry' to jump to its fallthrough, which was a landing pad. This results in 'entry' jumping to 2 different landing pads, which fails the machine verifier. rdar://problem/20750162 llvm-svn: 236248
* [ARM] Do not generate invalid encoding for stack adjust, even if this is justQuentin Colombet2015-04-301-2/+7
| | | | | | | | | | | | | temporary. Because of that: 1. The machine verifier was complaining on such code. 2. The generate code worked just because the thumb reduction size pass fixed the opcode. rdar://problem/20749824 llvm-svn: 236247
* AArch64: add BFC alias for the BFI/BFM instructions.Tim Northover2015-04-302-4/+69
| | | | | | | | | Unlike 32-bit ARM, AArch64 can use wzr/xzr to implement this without the need for a separate instruction. rdar://18679590 llvm-svn: 236245
* Add a note about permitting default member initializersReid Kleckner2015-04-301-4/+4
| | | | | | | Use them in WinEHPrepare so that we can spot any toolchain bugs that come up. llvm-svn: 236244
* Reinstate revisions r234755, r234759, r234760Jan Vesely2015-04-308-2/+92
| | | | | | | | | changes: Don't apply on hexagon and NVPTX since they no longer claim to support UADDO/USUBO Add location to getConstant Drop comment about the ops being turned into expand llvm-svn: 236240
* Write sections mostly in one pass.Rafael Espindola2015-04-301-143/+93
| | | | | | | | | | | During ELF writing, there is no need to further relax the sections, so we should not be creating fragments. This patch avoids doing so in all cases but debug section compression (that is next). Also, the ELF format is fairly simple to write. We can do a single pass over the sections to write them out and compute the section header table. llvm-svn: 236235
* Silencing an "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2015-04-301-1/+1
| | | | | | warning; NFC. llvm-svn: 236234
* Silence unused warning in non-assert builds.Daniel Jasper2015-04-301-2/+3
| | | | llvm-svn: 236213
* Inline local variable to silence unused warning.Daniel Jasper2015-04-301-2/+1
| | | | llvm-svn: 236212
* Masked gather and scatter - added DAGCombine visitorsElena Demikhovsky2015-04-306-45/+281
| | | | | | | | | and AVX-512 instruction selection patterns. All other patches, including tests will follow. http://reviews.llvm.org/D7665 llvm-svn: 236211
* [SSE] Fix for MUL v16i8 on pre-SSE41 targets (PR23369).Simon Pilgrim2015-04-301-4/+4
| | | | | | Sign extension of i8 to i16 was placing the unpacked bytes in the lower byte instead of the upper byte. llvm-svn: 236209
* [TableGen] Cleanup formatting by moving operators from beginning of line to ↵Craig Topper2015-04-302-43/+40
| | | | | | end of previous line. NFC llvm-svn: 236206
* [TableGen] Used range-based for loop. NFC.Craig Topper2015-04-301-6/+2
| | | | llvm-svn: 236205
* [TableGen] Merge a variable assignment and a return to drop curly braces. ↵Craig Topper2015-04-301-13/+7
| | | | | | Fold an assignment into an if. Use auto on the result of a couple dyn_casts. NFC llvm-svn: 236204
* [InstCombine] Add new rule for MIN(MAX(~A, ~B), ~C) et. al.Sanjoy Das2015-04-301-0/+86
| | | | | | | | | | | | | | | | | Summary: Optimizing these well are especially interesting for IRCE since it "clamps" values by generating this sort of pattern through SCEV expressions. Depends on D9352. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9353 llvm-svn: 236203
OpenPOWER on IntegriCloud