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* Split the usage of 'EVT PartVT' into 'MVT PartVT' and 'EVT PartEVT'.Patrik Hagglund2012-12-191-38/+38
| | | | llvm-svn: 170540
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-192-14/+13
| | | | | | instead of EVTs. llvm-svn: 170538
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-193-7/+6
| | | | | | MVTs, instead of EVTs. llvm-svn: 170537
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-192-14/+19
| | | | | | from EVT. llvm-svn: 170536
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-196-20/+20
| | | | | | EVTs. llvm-svn: 170535
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-191-4/+4
| | | | | | EVTs. llvm-svn: 170534
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-195-8/+8
| | | | | | of EVT. llvm-svn: 170532
* [msan] Heuristically instrument unknown intrinsics.Evgeniy Stepanov2012-12-191-1/+143
| | | | | | | | | | | | This changes adds shadow and origin propagation for unknown intrinsics by examining the arguments and ModRef behaviour. For now, only 3 classes of intrinsics are handled: - those that look like simple SIMD store - those that look like simple SIMD load - those that don't have memory effects and look like arithmetic/logic/whatever operation on simple types. llvm-svn: 170530
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-192-9/+9
| | | | | | instead of EVTs. llvm-svn: 170529
* LoopVectorize: Make iteration over induction variables not depend on pointer ↵Benjamin Kramer2012-12-191-4/+4
| | | | | | | | | | values. MapVector is a bit heavyweight, but I don't see a simpler way. Also the InductionList is unlikely to be large. This should help 3-stage selfhost compares (PR14647). llvm-svn: 170528
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-192-12/+15
| | | | llvm-svn: 170524
* X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]NAKAMURA Takumi2012-12-191-2/+2
| | | | llvm-svn: 170523
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-192-4/+4
| | | | | | EVT. llvm-svn: 170522
* Inline hasFunctionOnlyAttrs into its only use.Bill Wendling2012-12-191-1/+19
| | | | llvm-svn: 170518
* Inline the only use of the hasParameterOnlyAttrs method.Bill Wendling2012-12-191-1/+4
| | | | llvm-svn: 170517
* Inline the 'hasIncompatibleWithVarArgsAttrs' method into its only uses. And ↵Bill Wendling2012-12-192-2/+3
| | | | | | some minor comment reformatting. llvm-svn: 170516
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-192-3/+4
| | | | llvm-svn: 170510
* Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky2012-12-193-4/+104
| | | | llvm-svn: 170506
* After reducing the size of an operation in the DAG we zero-extend the reducedNadav Rotem2012-12-191-2/+5
| | | | | | | | bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-1972-529/+529
| | | | | | single attribute in the future. llvm-svn: 170502
* Remove more of 'else's after 'returns'. No functional change.Craig Topper2012-12-191-6/+6
| | | | llvm-svn: 170497
* Remove a bunch of 'else's after 'returns'Craig Topper2012-12-191-18/+18
| | | | llvm-svn: 170496
* Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be ↵Craig Topper2012-12-191-3/+9
| | | | | | rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
* Add some missing Defs and Uses.Reed Kotler2012-12-191-1/+11
| | | | llvm-svn: 170493
* Make sure the buffer, which containas an instance of APFloat, has proper ↵Shuxin Yang2012-12-191-7/+5
| | | | | | alignment. llvm-svn: 170486
* Add to the disassembler C API an option to print the disassembledKevin Enderby2012-12-182-0/+20
| | | | | | | | | | | | | | | | instructions in the assembly code variant if one exists. The intended use for this is so tools like lldb and darwin's otool(1) can be switched to print Intel-flavored disassembly. I discussed extensively this API with Jim Grosbach and we feel while it may not be fully general, in reality there is only one syntax for each assembly with the exception of X86 which has exactly two for historical reasons. rdar://10989182 llvm-svn: 170477
* Use bidirectional bundle flags to simplify important functions.Jakob Stoklund Olesen2012-12-181-10/+0
| | | | | | | | | | | The bundle_iterator::operator++ function now doesn't need to dig out the basic block and check against end(). It can use the isBundledWithSucc() flag to find the last bundled instruction safely. Similarly, MachineInstr::isBundled() no longer needs to look at iterators etc. It only has to look at flags. llvm-svn: 170473
* rdar://12801297 Shuxin Yang2012-12-181-0/+715
| | | | | | InstCombine for unsafe floating-point add/sub. llvm-svn: 170471
* Enable the loop vectorizer in clang and not in the pass manager, so that we ↵Nadav Rotem2012-12-181-1/+1
| | | | | | can disable it in clang. llvm-svn: 170470
* Verify bundle flag consistency when setting them.Jakob Stoklund Olesen2012-12-181-0/+4
| | | | | | | Now that the bundle flag aware APIs are all in place, it is possible to continuously verify the flag consistency. llvm-svn: 170465
* Reverse order of checking SSE level when calculating compare cost, so we checkJakub Staszak2012-12-181-6/+6
| | | | | | AVX2 before AVX. llvm-svn: 170464
* Verify bundle flags for consistency in MachineVerifier.Jakob Stoklund Olesen2012-12-181-0/+17
| | | | | | | The new bidirectional bundle flags are redundant, so inadvertent bundle tearing can be detected in the machine code verifier. llvm-svn: 170463
* Disable ARM partial flag dependency optimization at -OzQuentin Colombet2012-12-181-2/+10
| | | | | | | | To not over constrain the scheduler for ARM in thumb mode, some optimizations for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency). Disables this check when code size is the priority, i.e., code is compiled with -Oz. llvm-svn: 170462
* Don't allow the automatically updated MI flags to be set directly.Jakob Stoklund Olesen2012-12-181-2/+2
| | | | | | | | | | | The bundle-related MI flags need to be kept in sync with the neighboring instructions. Don't allow the bulk flag-setting setFlags() function to change them. Also don't copy MI flags when cloning an instruction. The clone's bundle flags will be set when it is explicitly inserted into a bundle. llvm-svn: 170459
* Tighten up the splice() API for bundled instructions.Jakob Stoklund Olesen2012-12-181-13/+0
| | | | | | | | | | | Remove the instr_iterator versions of the splice() functions. It doesn't seem useful to be able to splice sequences of instructions that don't consist of full bundles. The normal splice functions that take MBB::iterator arguments are not changed, and they can move whole bundles around without any problems. llvm-svn: 170456
* MISched: add dependence to ExitSU to model live-out latency.Andrew Trick2012-12-181-1/+16
| | | | llvm-svn: 170454
* MISched: Cleanup, redundant statement.Andrew Trick2012-12-181-1/+0
| | | | llvm-svn: 170453
* MISched: Heuristics, compare latency more precisely. It matters more for ↵Andrew Trick2012-12-181-43/+38
| | | | | | some targets. llvm-svn: 170452
* MISched: Remove SchedRemainder::IsResourceLimited. I don't know how to ↵Andrew Trick2012-12-181-3/+0
| | | | | | compute it. llvm-svn: 170451
* MISched: cleanup, use the proper iterator type.Andrew Trick2012-12-181-1/+1
| | | | llvm-svn: 170450
* MISched: minor improvement, initialize remaining resources before the first ↵Andrew Trick2012-12-181-0/+10
| | | | | | scheduling decision. llvm-svn: 170449
* LoopVectorize: Emit reductions as log2(vectorsize) shuffles + vector ops ↵Benjamin Kramer2012-12-181-12/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead of scalar operations. For example on x86 with SSE4.2 a <8 x i8> add reduction becomes movdqa %xmm0, %xmm1 movhlps %xmm1, %xmm1 ## xmm1 = xmm1[1,1] paddw %xmm0, %xmm1 pshufd $1, %xmm1, %xmm0 ## xmm0 = xmm1[1,0,0,0] paddw %xmm1, %xmm0 phaddw %xmm0, %xmm0 pextrb $0, %xmm0, %edx instead of pextrb $2, %xmm0, %esi pextrb $0, %xmm0, %edx addb %sil, %dl pextrb $4, %xmm0, %esi addb %dl, %sil pextrb $6, %xmm0, %edx addb %sil, %dl pextrb $8, %xmm0, %esi addb %dl, %sil pextrb $10, %xmm0, %edi pextrb $14, %xmm0, %edx addb %sil, %dil pextrb $12, %xmm0, %esi addb %dil, %sil addb %sil, %dl llvm-svn: 170439
* Get rid of the pesky -Woverloaded-virtual warning. No change in functionality.Eli Bendersky2012-12-182-0/+5
| | | | llvm-svn: 170438
* Tighten the insert() API for bundled instructions.Jakob Stoklund Olesen2012-12-181-0/+12
| | | | | | | | | | | | | | | | | The normal insert() function takes an MBB::iterator position, and inserts a stand-alone MachineInstr as before. The insert() function that takes an MBB::instr_iterator position can insert instructions inside a bundle, and will now update the bundle flags correctly when that happens. When the insert position is between two bundles, it is unclear whether the instruction should be appended to the previous bundle, prepended to the next bundle, or stand on its own. The MBB::insert() function doesn't bundle the instruction in that case, use the MIBundleBuilder class for that. llvm-svn: 170437
* Check multiple register classes for inline asm tied registersHal Finkel2012-12-181-3/+16
| | | | | | | | | | | | | | | | | | A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
* Enable the loop vectorizer.Nadav Rotem2012-12-181-1/+1
| | | | llvm-svn: 170416
* SROA: Replace calls to getScalarSizeInBits to DataLayout's API becauseNadav Rotem2012-12-181-6/+6
| | | | | | getScalarSizeInBits could not handle vectors of pointers. llvm-svn: 170412
* Initialize NoRedZone and remove unused default values.Rafael Espindola2012-12-181-3/+4
| | | | llvm-svn: 170404
* Repair bundles that were broken by removing and reinserting the firstJakob Stoklund Olesen2012-12-181-1/+8
| | | | | | | | | | instruction. This isn't strictly necessary at the moment because Thumb2SizeReduction also copies all MI flags from the old instruction to the new. However, a future patch will make that kind of direct flag tampering illegal. llvm-svn: 170395
* Formatting.Eric Christopher2012-12-181-1/+1
| | | | llvm-svn: 170394
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